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    Multi-socket network interface controller with consistent transaction ordering
    1.
    发明授权
    Multi-socket network interface controller with consistent transaction ordering 有权

    公开(公告)号：US12259832B2

    公开(公告)日：2025-03-25

    申请号：US18174668

    申请日：2023-02-27

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Tzahi Oved ,  Achiad Shochat ,  Liran Liss ,  Noam Bloch ,  Aviv Heller ,  Idan Burstein ,  Ariel Shahar ,  Peter Paneah

    IPC: G06F13/28 ,  G06F3/06

    Abstract: Computing apparatus includes a host computer, including multiple non-uniform memory access (NUMA) nodes, including at least first and second NUMA nodes, which include first and second local memories and first and second host bus interfaces for connection to first and second peripheral component buses, respectively. A network interface controller (NIC) is to receive a definition of a memory region extending over respective first and second parts of the first and second local memories and to receive a memory mapping with respect to the memory region that is applicable to both the first and second local memories, and to apply the memory mapping in writing data to the memory region via first and second NIC bus interfaces in a sequence of direct memory access (DMA) transactions to the respective first and second parts of the first and second local memories in response to packets received through a network port.

    Efficient Scatter-Gather Over an Uplink
    2.
    发明申请
    Efficient Scatter-Gather Over an Uplink 审中-公开

    公开(公告)号：US20190149486A1

    公开(公告)日：2019-05-16

    申请号：US16181376

    申请日：2018-11-06

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Dror Bohrer ,  Noam Bloch ,  Peter Paneah ,  Richard Graham

    IPC: H04L12/879 ,  H04L12/883 ,  H04L12/861 ,  H04L12/935

    Abstract: A network interface device is connected to a host computer by having a memory controller, and a scatter-gather offload engine linked to the memory controller. The network interface device prepares a descriptor including a plurality of specified memory locations in the host computer, incorporates the descriptor in exactly one upload packet, transmits the upload packet to the scatter-gather offload engine via the uplink, invokes the scatter-gather offload engine to perform memory access operations cooperatively with the memory controller at the specified memory locations of the descriptor, and accepts results of the memory access operations.

    Multi-socket network interface controller with consistent transaction ordering
    4.
    发明申请
    Multi-socket network interface controller with consistent transaction ordering 有权

    公开(公告)号：US20220358063A1

    公开(公告)日：2022-11-10

    申请号：US17503392

    申请日：2021-10-18

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Tzahi Oved ,  Achiad Shochat ,  Liran Liss ,  Noam Bloch ,  Aviv Heller ,  Idan Burstein ,  Ariel Shahar ,  Peter Paneah

    IPC: G06F13/28 ,  G06F3/06

    Abstract: Computing apparatus includes a host computer, including at least first and second host bus interfaces. A network interface controller (NIC) includes a network port, for connection to a packet communication network, and first and second NIC bus interfaces, which communicate via first and second peripheral component buses with the first and second host bus interfaces, respectively. Packet processing logic, in response to packets received through the network port, writes data to the host memory concurrently via both the first and second NIC bus interfaces in a sequence of direct memory access (DMA) transactions, and after writing the data in any given DMA transaction, writes a completion report to the host memory with respect to the given DMA transaction while verifying that the completion report will be available to the CPU only after all the data in the given DMA transaction have been written to the host memory.

    Dual purpose NIC/PCIe protocol logic analyzer
    5.
    发明授权
    Dual purpose NIC/PCIe protocol logic analyzer 有权

    公开(公告)号：US11218397B2

    公开(公告)日：2022-01-04

    申请号：US16258600

    申请日：2019-01-27

    Applicant: Mellanox Technologies, Ltd.

    Inventor： Peter Paneah ,  Yoni Galezer ,  Vladimir Vainer

    IPC: G06F13/42 ,  H04L12/26 ,  G06F11/30 ,  G06F11/36 ,  G06F13/40

    Abstract: An apparatus includes a processor, a first interface configured to connect to a bus of the apparatus, a second interface configured to communicate over a packet network, and circuitry. The circuitry is configured to, in a first operational mode, exchange data between the processor and one or more remote devices over the packet network, via the second interface, and in a second operational mode, monitor the bus using the first interface, detect a predefined trigger event occurring on the bus and, in response to detecting the trigger event, log one or more transactions on the bus that are adjacent to the trigger event and generate one or more protocol-analysis packets comprising at least part of the logged transactions.

    Dual Purpose NIC/PCIe Protocol Logic Analyzer
    6.
    发明申请
    Dual Purpose NIC/PCIe Protocol Logic Analyzer 审中-公开

    公开(公告)号：US20200244562A1

    公开(公告)日：2020-07-30

    申请号：US16258600

    申请日：2019-01-27

    Applicant: Mellanox Technologies, Ltd.

    Inventor： Peter Paneah ,  Yoni Galezer ,  Vladimir Vainer

    IPC: H04L12/26 ,  G06F11/30 ,  G06F11/36 ,  G06F13/40 ,  G06F13/42

    Abstract: An apparatus includes a processor, a first interface configured to connect to a bus of the apparatus, a second interface configured to communicate over a packet network, and circuitry. The circuitry is configured to, in a first operational mode, exchange data between the processor and one or more remote devices over the packet network, via the second interface, and in a second operational mode, monitor the bus using the first interface, detect a predefined trigger event occurring on the bus and, in response to detecting the trigger event, log one or more transactions on the bus that are adjacent to the trigger event and generate one or more protocol-analysis packets comprising at least part of the logged transactions.

    Efficient scatter-gather over an uplink
    8.
    发明授权
    Efficient scatter-gather over an uplink 有权

    公开(公告)号：US10887252B2

    公开(公告)日：2021-01-05

    申请号：US16181376

    申请日：2018-11-06

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Dror Bohrer ,  Noam Bloch ,  Peter Paneah ,  Richard Graham

    IPC: G06F15/167 ,  H04L12/879 ,  H04L12/883 ,  H04L12/931 ,  H04L12/861 ,  H04L12/935

    Abstract: A network interface device is connected to a host computer by having a memory controller, and a scatter-gather offload engine linked to the memory controller. The network interface device prepares a descriptor including a plurality of specified memory locations in the host computer, incorporates the descriptor in exactly one upload packet, transmits the upload packet to the scatter-gather offload engine via the uplink, invokes the scatter-gather offload engine to perform memory access operations cooperatively with the memory controller at the specified memory locations of the descriptor, and accepts results of the memory access operations.

    FACILITATING VIRTUAL FUNCTIONS USING MEMORY ALLOCATION IN A VIRTUALIZATION ENVIRONMENT
    9.
    发明申请
    FACILITATING VIRTUAL FUNCTIONS USING MEMORY ALLOCATION IN A VIRTUALIZATION ENVIRONMENT 审中-公开

    公开(公告)号：US20190332291A1

    公开(公告)日：2019-10-31

    申请号：US15963236

    申请日：2018-04-26

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Ariel Shahar ,  Peter Paneah ,  Maxim ZABOROV

    IPC: G06F3/06 ,  G06F13/16

    Abstract: Apparatuses and methods are described that provide for a mechanism for allocating physical device memory for one or more virtual functions. In particular, a memory allocating framework is provided to utilize device memory more efficiently by mapping at least one target location of the physical memory in a Base Address Register (BAR) associated with the virtual function from a plurality of available target locations based on an allocation request. The memory allocating framework is further configured to compare an indication associated with the requesting virtual function to an identifier of the requested target location. Moreover, the memory allocating framework is further configured to allow the simultaneous use of more than one virtual function at a time while providing isolation between multiple virtual functions.

    Trusted out-of-band memory acquisition for IOMMU-based computer systems
    10.
    发明申请
    Trusted out-of-band memory acquisition for IOMMU-based computer systems 审中-公开

    公开(公告)号：US20190310945A1

    公开(公告)日：2019-10-10

    申请号：US15947816

    申请日：2018-04-08

    Applicant: Mellanox Technologies, Ltd.

    Inventor： Ahmad Atamlh ,  Ofir Arkin ,  Peter Paneah

    IPC: G06F12/10 ,  G06F13/10 ,  G06F13/16 ,  G06F13/20 ,  G06F13/42

    Abstract: An apparatus includes an interface and memory acquisition circuitry. The interface is configured to communicate over a bus operating in accordance with a bus protocol, which supports address-translation transactions that translate between bus addresses in an address space of the bus and physical memory addresses in an address space of a memory. The memory acquisition circuitry is configured to read data from the memory by issuing over the bus, using the bus protocol, one or more requests that (i) specify addresses to be read in terms of the physical memory addresses, and (ii) indicate that the physical memory addresses in the requests have been translated from corresponding bus addresses even though the addresses were not obtained by any address-translation transaction over the bus.

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