System and method of noise correcting PLL frequency synthesizers

    公开(公告)号:US09793904B1

    公开(公告)日:2017-10-17

    申请号:US15469434

    申请日:2017-03-24

    CPC classification number: H03L7/087 H03K5/1252 H03L7/099 H03L7/18

    Abstract: An improved noise-corrected phase-locked loop frequency synthesizer configured to reduce noise, such as phase noise and spurious signals, without the use of switching circuits. The synthesizer uses a phase shifter device configured to accept a noise containing frequency signal from a voltage controlled oscillator (VCO) circuit, such as an integer-N single loop PLL synthesizer, as well as noise reducing control signals from a noise detecting sensor or circuit, and output a noise reduced VCO frequency signal. In some embodiments, the noise reducing sensor may be formed from a second, lower noise, phase locked loop circuit. The frequency synthesizer circuit, noise detecting sensor, and the phase shifter device are configured to all run continuously, with the noise reducing sensor and frequency shifter continually acting to reduce noise, produced by higher noise integer-N PLL frequency synthesizer.

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