公开(公告)号：US20140246722A1

公开(公告)日：2014-09-04

申请号：US13784723

申请日：2013-03-04

Applicant: MICROCHIP TECHNOLOGY INCORPORATED

Inventor： Gregory Dix ,  Harold Kline ,  Dan Grimm ,  Roger Melcher ,  Jacob L. Williams

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/78 ,  H01L23/4824 ,  H01L23/5226 ,  H01L29/66477 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A power MOS field effect transistor (FET) has a plurality of transistor cells, each cell having a source region and a drain region to be contacted through a surface of a silicon wafer die. A first dielectric layer is disposed on the surface of the silicon wafer die and a plurality of grooves are formed in the first dielectric layer above the source regions and drain regions, respectively and filled with a conductive material. A second dielectric layer is disposed on a surface of the first dielectric layer and has openings to expose contact areas to said grooves. A metal layer is disposed on a surface of the second dielectric layer and filling the openings, wherein the metal layer is patterned and etched to form separate metal wires connecting each drain region and each source region of the plurality of transistor cells, respectively through the grooves.

Abstract translation: 功率MOS场效应晶体管（FET）具有多个晶体管单元，每个单元具有通过硅晶片管芯的表面接触的源极区域和漏极区域。 第一电介质层设置在硅晶片管芯的表面上，分别在源极区和漏极区之上的第一电介质层中分别形成多个沟槽并填充导电材料。 第二电介质层设置在第一电介质层的表面上，并且具有露出与所述沟槽接触区域的开口。 金属层设置在第二电介质层的表面上并填充开口，其中对金属层进行图案化和蚀刻，以形成分别连接多个晶体管单元的漏极区域和每个源极区域的金属线路，该金属线路通过沟槽 。

公开(公告)号：US08937351B2

公开(公告)日：2015-01-20

申请号：US13784723

申请日：2013-03-04

Applicant: Microchip Technology Incorporated

Inventor： Gregory Dix ,  Harold Kline ,  Dan Grimm ,  Roger Melcher ,  Jacob L. Williams

IPC: H01L29/66 ,  H01L29/78 ,  H01L23/522

CPC classification number: H01L29/78 ,  H01L23/4824 ,  H01L23/5226 ,  H01L29/66477 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A power metal-oxide-semiconductor (MOS) field effect transistor (FET) has a plurality of transistor cells, each cell having a source region and a drain region to be contacted through a surface of a silicon wafer die, A first dielectric layer is disposed on the surface of the silicon wafer die and a plurality of grooves are formed in the first dielectric layer above the source regions and drain regions, respectively and filled with a conductive material, A second dielectric layer is disposed on a surface of the first dielectric layer and has openings to expose contact areas to the grooves. A metal layer is disposed on a surface of the second dielectric layer and filling the openings, wherein the metal layer is patterned and etched to form separate metal wires connecting each drain region and each source region of the plurality of transistor cells, respectively through the grooves.

Abstract translation: 功率金属氧化物半导体（MOS）场效应晶体管（FET）具有多个晶体管单元，每个单元具有通过硅晶片管芯的表面接触的源区和漏区，第一介电层为 设置在硅晶片模具的表面上，并且在源极区域和漏极区域上方的第一电介质层中分别形成有多个沟槽，并且填充有导电材料。第二电介质层设置在第一电介质的表面上 并且具有用于将接触区域暴露于凹槽的开口。 金属层设置在第二电介质层的表面上并填充开口，其中对金属层进行图案化和蚀刻，以形成分别连接多个晶体管单元的漏极区域和每个源极区域的金属线路，该金属线路通过沟槽 。