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    Power field effect transistor
    1.
    发明授权
    Power field effect transistor 有权

    公开(公告)号：US09634135B2

    公开(公告)日：2017-04-25

    申请号：US13778301

    申请日：2013-02-27

    Applicant: Microchip Technology Incorporated

    Inventor： Greg A. Dix ,  Dan Grimm

    IPC: H01L29/778 ,  H01L29/78 ,  H01L29/417 ,  H01L29/45 ,  H01L29/08

    CPC classification number: H01L29/7809 ,  H01L29/0878 ,  H01L29/41766 ,  H01L29/456 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A field-effect transistors (FET) cell structure has a substrate, an epitaxial layer of a first conductivity type on the substrate, first and second base regions of the second conductivity type arranged within the epitaxial layer or well and spaced apart, and first and second source regions of a first conductivity type arranged within the first and second base region, respectively. Furthermore, a gate structure insulated from the epitaxial layer by an insulation layer is provided and arranged above the region between the first and second base regions and covering at least partly the first and second base region, and a drain contact reaches from a top of the device through the epitaxial layer to couple a top contact or metal layer with the substrate.

    POWER FIELD EFFECT TRANSISTOR
    3.
    发明申请
    POWER FIELD EFFECT TRANSISTOR 有权
    功率场效应晶体管

    公开(公告)号：US20130228854A1

    公开(公告)日：2013-09-05

    申请号：US13778301

    申请日：2013-02-27

    Applicant: MICROCHIP TECHNOLOGY INCORPORATED

    Inventor： Greg A. Dix ,  Dan Grimm

    IPC: H01L29/78

    CPC classification number: H01L29/7809 ,  H01L29/0878 ,  H01L29/41766 ,  H01L29/456 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A field-effect transistors (FET) cell structure has a substrate, an epitaxial layer of a first conductivity type on the substrate, first and second base regions of the second conductivity type arranged within the epitaxial layer or well and spaced apart, and first and second source regions of a first conductivity type arranged within the first and second base region, respectively. Furthermore, a gate structure insulated from the epitaxial layer by an insulation layer is provided and arranged above the region between the first and second base regions and covering at least partly the first and second base region, and a drain contact reaches from a top of the device through the epitaxial layer to couple a top contact or metal layer with the substrate.

    Abstract translation: 场效应晶体管（FET）单元结构具有衬底，衬底上具有第一导电类型的外延层，第二导电类型的第一和第二基极区布置在外延层内或阱内并且间隔开，以及第一和第 第一导电类型的第二源极区域分别布置在第一和第二基极区域内。 此外，通过绝缘层与外延层绝缘的栅极结构被设置并布置在第一和第二基极区域之间的区域上方并且至少部分地覆盖第一和第二基极区域，并且漏极接触从顶部 器件通过外延层将顶部接触或金属层与衬底耦合。

    Power MOS Transistor with Improved Metal Contact
    4.
    发明申请
    Power MOS Transistor with Improved Metal Contact 有权
    功率MOS晶体管，具有改进的金属接触

    公开(公告)号：US20140246722A1

    公开(公告)日：2014-09-04

    申请号：US13784723

    申请日：2013-03-04

    Applicant: MICROCHIP TECHNOLOGY INCORPORATED

    Inventor： Gregory Dix ,  Harold Kline ,  Dan Grimm ,  Roger Melcher ,  Jacob L. Williams

    IPC: H01L29/78 ,  H01L29/66

    CPC classification number: H01L29/78 ,  H01L23/4824 ,  H01L23/5226 ,  H01L29/66477 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A power MOS field effect transistor (FET) has a plurality of transistor cells, each cell having a source region and a drain region to be contacted through a surface of a silicon wafer die. A first dielectric layer is disposed on the surface of the silicon wafer die and a plurality of grooves are formed in the first dielectric layer above the source regions and drain regions, respectively and filled with a conductive material. A second dielectric layer is disposed on a surface of the first dielectric layer and has openings to expose contact areas to said grooves. A metal layer is disposed on a surface of the second dielectric layer and filling the openings, wherein the metal layer is patterned and etched to form separate metal wires connecting each drain region and each source region of the plurality of transistor cells, respectively through the grooves.

    Abstract translation: 功率MOS场效应晶体管（FET）具有多个晶体管单元，每个单元具有通过硅晶片管芯的表面接触的源极区域和漏极区域。 第一电介质层设置在硅晶片管芯的表面上，分别在源极区和漏极区之上的第一电介质层中分别形成多个沟槽并填充导电材料。 第二电介质层设置在第一电介质层的表面上，并且具有露出与所述沟槽接触区域的开口。 金属层设置在第二电介质层的表面上并填充开口，其中对金属层进行图案化和蚀刻，以形成分别连接多个晶体管单元的漏极区域和每个源极区域的金属线路，该金属线路通过沟槽 。

    Combined source and base contact for a field effect transistor
    5.
    发明授权
    Combined source and base contact for a field effect transistor 有权

    公开(公告)号：US10446497B2

    公开(公告)日：2019-10-15

    申请号：US15471726

    申请日：2017-03-28

    Applicant: Microchip Technology Incorporated

    Inventor： Dan Grimm ,  Gregory Dix

    IPC: H01L29/78 ,  H01L23/535 ,  H01L21/265 ,  H01L21/283 ,  H01L21/311 ,  H01L21/768 ,  H01L25/065 ,  H01L29/417 ,  H01L29/66 ,  H01L29/06 ,  H01L23/00 ,  H01L27/092

    Abstract: The present disclosure relates to semiconductor devices. The teachings thereof may be embodied in metal oxide semiconductor field effect transistors (MOSFET) and methods for their manufacture. Some embodiments may include: depositing a base within an epitaxial layer; implanting a source implant extending into the base, wherein the epitaxial layer, the base, and the source implant form a continuous plane surface; depositing an insulating layer on the continuous plane surface forming a gate in contact with both the epitaxial layer and the base; opening a contact groove through the insulating layer to expose a central portion of the source implant; depositing a layer of photoresist on top of the insulating layer above exposed portions of the source implant; patterning a set of stripes in the photoresist, each stripe perpendicular to the contact groove; etching the set of stripes with an etch chemistry selective to the insulating layer; and filling the contact groove with a conductive material creating a base-source contact groove reaching through the insulating layer to the surface of the source implant and comprising a plurality of sections spaced apart from each other reaching through the source implant into the base.

    Power MOS transistor with improved metal contact
    7.
    发明授权
    Power MOS transistor with improved metal contact 有权
    功率MOS晶体管具有改善的金属接触

    公开(公告)号：US08937351B2

    公开(公告)日：2015-01-20

    申请号：US13784723

    申请日：2013-03-04

    Applicant: Microchip Technology Incorporated

    Inventor： Gregory Dix ,  Harold Kline ,  Dan Grimm ,  Roger Melcher ,  Jacob L. Williams

    IPC: H01L29/66 ,  H01L29/78 ,  H01L23/522

    CPC classification number: H01L29/78 ,  H01L23/4824 ,  H01L23/5226 ,  H01L29/66477 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A power metal-oxide-semiconductor (MOS) field effect transistor (FET) has a plurality of transistor cells, each cell having a source region and a drain region to be contacted through a surface of a silicon wafer die, A first dielectric layer is disposed on the surface of the silicon wafer die and a plurality of grooves are formed in the first dielectric layer above the source regions and drain regions, respectively and filled with a conductive material, A second dielectric layer is disposed on a surface of the first dielectric layer and has openings to expose contact areas to the grooves. A metal layer is disposed on a surface of the second dielectric layer and filling the openings, wherein the metal layer is patterned and etched to form separate metal wires connecting each drain region and each source region of the plurality of transistor cells, respectively through the grooves.

    Abstract translation: 功率金属氧化物半导体（MOS）场效应晶体管（FET）具有多个晶体管单元，每个单元具有通过硅晶片管芯的表面接触的源区和漏区，第一介电层为 设置在硅晶片模具的表面上，并且在源极区域和漏极区域上方的第一电介质层中分别形成有多个沟槽，并且填充有导电材料。第二电介质层设置在第一电介质的表面上 并且具有用于将接触区域暴露于凹槽的开口。 金属层设置在第二电介质层的表面上并填充开口，其中对金属层进行图案化和蚀刻，以形成分别连接多个晶体管单元的漏极区域和每个源极区域的金属线路，该金属线路通过沟槽 。

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