公开(公告)号：US09972578B2

公开(公告)日：2018-05-15

申请号：US15471889

申请日：2017-03-28

Applicant: Microchip Technology Incorporated

Inventor： Gregory Dix ,  Lee Furey ,  Rohan Raghunathan

IPC: H01L23/00 ,  H01L23/552 ,  H01L25/065 ,  H01L23/31 ,  H01L23/495

CPC classification number: H01L23/552 ,  H01L23/3171 ,  H01L23/4951 ,  H01L23/49541 ,  H01L23/49575 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/16 ,  H01L2224/16245 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/48245 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2924/00014 ,  H01L2224/45099

Abstract: The present disclosure relates to semiconductor devices. Embodiments of the teachings thereof may include processes for manufacturing of semiconductor devices and the devices themselves. For example, some embodiments may include an integrated circuit package comprising: a lead frame; a first die mounted on the lead frame in flip-chip fashion, with a frontside of the first die connected to the lead frame; wherein the first die comprises an oxide layer deposited on a backside of the first die and a back metal layer deposited on the oxide layer; and a second die mounted on the back metal layer of the first die.

公开(公告)号：US08921986B2

公开(公告)日：2014-12-30

申请号：US13831682

申请日：2013-03-15

Applicant: Microchip Technology Incorporated

Inventor： Gregory Dix ,  Roger Melcher

IPC: H01L23/495

CPC classification number: H01L23/4952 ,  H01L23/3171 ,  H01L23/4824 ,  H01L23/4951 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/48 ,  H01L24/49 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/05567 ,  H01L2224/05647 ,  H01L2224/1148 ,  H01L2224/13014 ,  H01L2224/13021 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/1403 ,  H01L2224/14133 ,  H01L2224/14163 ,  H01L2224/16112 ,  H01L2224/16245 ,  H01L2224/17107 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/81191 ,  H01L2224/81801 ,  H01L2224/8185 ,  H01L2924/00014 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: A semiconductor power chip, may have a semiconductor die having a power device fabricated on a substrate thereof, wherein the power device has at least one first contact element, a plurality of second contact elements and a plurality of third contact elements arranged on top of the semiconductor die; and an insulation layer disposed on top of the semiconductor die and being patterned to provide openings to access the plurality of second and third contact elements and the at least one first contact element.

Abstract translation: 半导体功率芯片可以具有在其基板上制造的功率器件的半导体管芯，其中功率器件具有至少一个第一接触元件，多个第二接触元件和布置在其上的多个第三接触元件 半导体芯片; 以及绝缘层，其设置在所述半导体管芯的顶部上并被图案化以提供开口以接近所述多个第二和第三接触元件和所述至少一个第一接触元件。

公开(公告)号：US20140264796A1

公开(公告)日：2014-09-18

申请号：US13831682

申请日：2013-03-15

Applicant: MICROCHIP TECHNOLOGY INCORPORATED

Inventor： Gregory Dix ,  Roger Melcher

IPC: H01L23/495

CPC classification number: H01L23/4952 ,  H01L23/3171 ,  H01L23/4824 ,  H01L23/4951 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/48 ,  H01L24/49 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/05567 ,  H01L2224/05647 ,  H01L2224/1148 ,  H01L2224/13014 ,  H01L2224/13021 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/1403 ,  H01L2224/14133 ,  H01L2224/14163 ,  H01L2224/16112 ,  H01L2224/16245 ,  H01L2224/17107 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/81191 ,  H01L2224/81801 ,  H01L2224/8185 ,  H01L2924/00014 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: A semiconductor power chip, may have a semiconductor die having a power device fabricated on a substrate thereof, wherein the power device has at least one first contact element, a plurality of second contact elements and a plurality of third contact elements arranged on top of the semiconductor die; and an insulation layer disposed on top of the semiconductor die and being patterned to provide openings to access the plurality of second and third contact elements and the at least one first contact element.

Abstract translation: 半导体功率芯片可以具有在其基板上制造的功率器件的半导体管芯，其中功率器件具有至少一个第一接触元件，多个第二接触元件和布置在其上的多个第三接触元件 半导体芯片; 以及绝缘层，其设置在所述半导体管芯的顶部上并被图案化以提供开口以接近所述多个第二和第三接触元件和所述至少一个第一接触元件。

公开(公告)号：US20170287850A1

公开(公告)日：2017-10-05

申请号：US15471889

申请日：2017-03-28

Applicant: Microchip Technology Incorporated

Inventor： Gregory Dix ,  Lee Furey ,  Rohan Raghunathan

IPC: H01L23/552 ,  H01L23/495 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/552 ,  H01L23/3171 ,  H01L23/4951 ,  H01L23/49541 ,  H01L23/49575 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/16 ,  H01L2224/16245 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/48245 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2924/00014 ,  H01L2224/45099

Abstract: The present disclosure relates to semiconductor devices. Embodiments of the teachings thereof may include processes for manufacturing of semiconductor devices and the devices themselves. For example, some embodiments may include an integrated circuit package comprising: a lead frame; a first die mounted on the lead frame in flip-chip fashion, with a frontside of the first die connected to the lead frame; wherein the first die comprises an oxide layer deposited on a backside of the first die and a back metal layer deposited on the oxide layer; and a second die mounted on the back metal layer of the first die.

公开(公告)号：US20140246722A1

公开(公告)日：2014-09-04

申请号：US13784723

申请日：2013-03-04

Applicant: MICROCHIP TECHNOLOGY INCORPORATED

Inventor： Gregory Dix ,  Harold Kline ,  Dan Grimm ,  Roger Melcher ,  Jacob L. Williams

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/78 ,  H01L23/4824 ,  H01L23/5226 ,  H01L29/66477 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A power MOS field effect transistor (FET) has a plurality of transistor cells, each cell having a source region and a drain region to be contacted through a surface of a silicon wafer die. A first dielectric layer is disposed on the surface of the silicon wafer die and a plurality of grooves are formed in the first dielectric layer above the source regions and drain regions, respectively and filled with a conductive material. A second dielectric layer is disposed on a surface of the first dielectric layer and has openings to expose contact areas to said grooves. A metal layer is disposed on a surface of the second dielectric layer and filling the openings, wherein the metal layer is patterned and etched to form separate metal wires connecting each drain region and each source region of the plurality of transistor cells, respectively through the grooves.

Abstract translation: 功率MOS场效应晶体管（FET）具有多个晶体管单元，每个单元具有通过硅晶片管芯的表面接触的源极区域和漏极区域。 第一电介质层设置在硅晶片管芯的表面上，分别在源极区和漏极区之上的第一电介质层中分别形成多个沟槽并填充导电材料。 第二电介质层设置在第一电介质层的表面上，并且具有露出与所述沟槽接触区域的开口。 金属层设置在第二电介质层的表面上并填充开口，其中对金属层进行图案化和蚀刻，以形成分别连接多个晶体管单元的漏极区域和每个源极区域的金属线路，该金属线路通过沟槽 。

公开(公告)号：US20130154017A1

公开(公告)日：2013-06-20

申请号：US13709342

申请日：2012-12-10

Applicant: Microchip Technology Incorporated

Inventor： Gregory Dix ,  Harold Kline ,  Rodney Schroeder ,  Daniel J. Grimm

IPC: H01L27/088 ,  H01L29/66

CPC classification number: H01L27/088 ,  H01L21/2815 ,  H01L29/42376 ,  H01L29/66477 ,  H01L29/66712 ,  H01L29/7802

Abstract: A field effect transistor has a substrate with an epitaxial layer, base regions extending from a top of the epitaxial layer into the epitaxial layer, an insulation region having side walls and extending between two base regions on top of the substrate; and a polysilicon gate structure covering the insulation region including the side walls, wherein effective gates are formed by a portion of the polysilicon covering side walls above the base region.

Abstract translation: 场效应晶体管具有具有外延层的衬底，从外延层的顶部延伸到外延层中的基极区域，具有侧壁并在衬底顶部的两个基极区域之间延伸的绝缘区域; 以及覆盖包括侧壁的绝缘区域的多晶硅栅极结构，其中有效栅极由位于基极区域上方的多晶硅覆盖侧壁的一部分形成。

公开(公告)号：US20170287835A1

公开(公告)日：2017-10-05

申请号：US15471726

申请日：2017-03-28

Applicant: Microchip Technology Incorporated

Inventor： Dan Grimm ,  Gregory Dix

IPC: H01L23/535 ,  H01L25/065 ,  H01L21/768 ,  H01L21/283 ,  H01L21/311 ,  H01L29/417 ,  H01L21/265

CPC classification number: H01L23/535 ,  H01L21/265 ,  H01L21/283 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76895 ,  H01L24/42 ,  H01L24/85 ,  H01L25/0655 ,  H01L27/0922 ,  H01L29/0696 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/41775 ,  H01L29/66727 ,  H01L29/7802

Abstract: The present disclosure relates to semiconductor devices. The teachings thereof may be embodied in metal oxide semiconductor field effect transistors (MOSFET) and methods for their manufacture. Some embodiments may include: depositing a base within an epitaxial layer; implanting a source implant extending into the base, wherein the epitaxial layer, the base, and the source implant form a continuous plane surface; depositing an insulating layer on the continuous plane surface forming a gate in contact with both the epitaxial layer and the base; opening a contact groove through the insulating layer to expose a central portion of the source implant; depositing a layer of photoresist on top of the insulating layer above exposed portions of the source implant; patterning a set of stripes in the photoresist, each stripe perpendicular to the contact groove; etching the set of stripes with an etch chemistry selective to the insulating layer; and filling the contact groove with a conductive material creating a base-source contact groove reaching through the insulating layer to the surface of the source implant and comprising a plurality of sections spaced apart from each other reaching through the source implant into the base.

公开(公告)号：US08988142B2

公开(公告)日：2015-03-24

申请号：US14198078

申请日：2014-03-05

Applicant: Microchip Technology Incorporated

Inventor： Randy Yach ,  Gregory Dix ,  Thomas Youbok Lee ,  Vincent Quiquempoix

IPC: G05F1/10 ,  G05F3/08 ,  H01L25/065 ,  H01L25/16 ,  H04L25/02 ,  H04L25/49 ,  H01L49/02

CPC classification number: G05F3/08 ,  H01L23/495 ,  H01L23/4951 ,  H01L23/49575 ,  H01L24/05 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0655 ,  H01L25/16 ,  H01L25/162 ,  H01L28/40 ,  H01L2224/02166 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/05638 ,  H01L2224/05647 ,  H01L2224/05657 ,  H01L2224/05666 ,  H01L2224/0568 ,  H01L2224/05681 ,  H01L2224/48091 ,  H01L2224/48111 ,  H01L2224/48137 ,  H01L2224/48195 ,  H01L2224/48247 ,  H01L2224/48265 ,  H01L2224/49107 ,  H01L2224/49109 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/10161 ,  H01L2924/10253 ,  H01L2924/181 ,  H01L2924/19104 ,  H01L2924/3011 ,  H02M3/33523 ,  H04L25/0266 ,  H04L25/4902 ,  H01L2224/45099 ,  H01L2924/01014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: High voltage rated isolation capacitors are formed on a face of a primary integrated circuit die. The isolation capacitors AC couple the primary integrated circuit in a first voltage domain to a second integrated circuit in a second voltage domain. The isolation capacitors DC isolate the primary integrated circuit from the second integrated circuit die. Isolated power transfer from the first voltage domain to the second voltage domain is provided through the high voltage rated isolation capacitors with an AC oscillator or PWM generator. The AC oscillator voltage amplitude may be increased for an increase in power through the high voltage rated isolation capacitors, and a larger value capacitor in the second voltage domain may provide for peak current demand from circuits in the second voltage domain.

Abstract translation: 在一次集成电路管芯的表面上形成高压额定绝缘电容器。 隔离电容器AC将第一电压域中的初级集成电路耦合到第二电压域中的第二集成电路。 隔离电容器将主集成电路与第二集成电路管芯隔离。 通过具有交流振荡器或PWM发生器的高压额定绝缘电容提供从第一电压域到第二电压域的隔离电源传输。 通过高压额定隔离电容器可以增加交流振荡器电压幅度以增加功率，并且第二电压域中的较大值的电容可以提供来自第二电压域中的电路的峰值电流需求。

公开(公告)号：US08896473B2

公开(公告)日：2014-11-25

申请号：US13897955

申请日：2013-05-20

Applicant: Microchip Technology Incorporated

Inventor： Gregory Dix

IPC: H03M1/66 ,  H03M1/06 ,  H03M1/78 ,  H03M1/76 ,  H03M1/68

CPC classification number: H03M1/785 ,  H03M1/06 ,  H03M1/682 ,  H03M1/765

Abstract: A digital-to analog-converter (DAC) has a MSB resistor ladder with a plurality of series connected resistors, wherein the MSB resistor ladder is coupled between a first and second reference potential, a LSB resistor ladder with a plurality of series connected resistors, and a plurality of switching units for connecting one of the series connected resistors of the MSB resistor ladder with the LSB resistor ladder, wherein each switching unit has a first switch for connecting a first terminal of an associated MSB resistor with a first terminal of the LSB resistor ladder and a second switch for connecting a second terminal of the associated MSB resistor with a second terminal of the LSB resistor ladder and wherein each switch is configured form a resistor of similar value of the resistors of the LSB resistor ladder when switched on.

Abstract translation: 数模转换器（DAC）具有带有多个串联电阻器的MSB电阻梯，其中MSB电阻器梯形耦合在第一和第二参考电位之间，LSB电阻梯与多个串联连接的电阻， 以及多个开关单元，用于将MSB电阻梯的串联电阻器中的一个连接到LSB电阻梯，其中每个开关单元具有用于将相关联的MSB电阻器的第一端子与LSB的第一端子连接的第一开关 电阻梯和第二开关，用于将相关联的MSB电阻器的第二端子连接到LSB电阻器的第二端子，并且其中每个开关被配置为当开关时LSB电阻器梯形电阻器的电阻值类似的电阻器。

公开(公告)号：US20140253227A1

公开(公告)日：2014-09-11

申请号：US14198078

申请日：2014-03-05

Applicant: Microchip Technology Incorporated

Inventor： Randy Yach ,  Gregory Dix ,  Thomas Youbok Lee ,  Vincent Quiquempoix

IPC: G05F3/08

CPC classification number: G05F3/08 ,  H01L23/495 ,  H01L23/4951 ,  H01L23/49575 ,  H01L24/05 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0655 ,  H01L25/16 ,  H01L25/162 ,  H01L28/40 ,  H01L2224/02166 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/05638 ,  H01L2224/05647 ,  H01L2224/05657 ,  H01L2224/05666 ,  H01L2224/0568 ,  H01L2224/05681 ,  H01L2224/48091 ,  H01L2224/48111 ,  H01L2224/48137 ,  H01L2224/48195 ,  H01L2224/48247 ,  H01L2224/48265 ,  H01L2224/49107 ,  H01L2224/49109 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/10161 ,  H01L2924/10253 ,  H01L2924/181 ,  H01L2924/19104 ,  H01L2924/3011 ,  H02M3/33523 ,  H04L25/0266 ,  H04L25/4902 ,  H01L2224/45099 ,  H01L2924/01014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: High voltage rated isolation capacitors are formed on a face of a primary integrated circuit die. The isolation capacitors AC couple the primary integrated circuit in a first voltage domain to a second integrated circuit in a second voltage domain. The isolation capacitors DC isolate the primary integrated circuit from the second integrated circuit die. Isolated power transfer from the first voltage domain to the second voltage domain is provided through the high voltage rated isolation capacitors with an AC oscillator or PWM generator. The AC oscillator voltage amplitude may be increased for an increase in power through the high voltage rated isolation capacitors, and a larger value capacitor in the second voltage domain may provide for peak current demand from circuits in the second voltage domain.

Abstract translation: 在一次集成电路管芯的表面上形成高压额定绝缘电容器。 隔离电容器AC将第一电压域中的初级集成电路耦合到第二电压域中的第二集成电路。 隔离电容器将主集成电路与第二集成电路管芯隔离。 通过具有交流振荡器或PWM发生器的高压额定绝缘电容提供从第一电压域到第二电压域的隔离电源传输。 通过高压额定隔离电容器可以增加交流振荡器电压幅度以增加功率，并且第二电压域中的较大值的电容可以提供来自第二电压域中的电路的峰值电流需求。