公开(公告)号：US08687435B2

公开(公告)日：2014-04-01

申请号：US13847189

申请日：2013-03-19

Applicant: Micron Technology, Inc.

Inventor： Scott N. Gatzemeier ,  Wallace E. Fister ,  Adam D. Johnson ,  Benjamin S. Louie

IPC: G11C7/10

CPC classification number: G11C7/10 ,  G11C5/066 ,  G11C29/1201 ,  G11C29/48 ,  G11C2029/2602

Abstract: Methods, memory devices and systems are disclosed. In one embodiment, a non-volatile memory device receives command signals through the same input/output terminals that receive address signals and write data signals and transmit read data signals. The input/output terminals are connected to a multiplexer, which is responsive to a received mode control signal to couple the input/output terminals to either a command bus or an input/output bus. A latch in the memory device latches the command signals when the mode control signal causes the input/output terminals to be coupled to the input/output bus. As a result, the command signals continue to be applied to the command bus. When the mode control signal causes the input/output terminals to be coupled to the input/output bus, write data signals are clocked into the memory device and read data signals are clocked out of the memory device responsive to a received clock signal.

Abstract translation: 公开了方法，存储器件和系统。 在一个实施例中，非易失性存储器件通过接收地址信号和写数据信号并发送读数据信号的相同输入/输出端接收命令信号。 输入/输出端连接到多路复用器，其响应于接收模式控制信号将输入/输出端子耦合到命令总线或输入/输出总线。 当模式控制信号使输入/输出端子耦合到输入/输出总线时，存储器件中的锁存器锁存命令信号。 结果，命令信号继续应用于命令总线。 当模式控制信号使得输入/输出端子耦合到输入/输出总线时，写数据信号被计时到存储器件中，并且响应于所接收的时钟信号将读出的数据信号从存储器件中输出。

公开(公告)号：US20130229878A1

公开(公告)日：2013-09-05

申请号：US13847189

申请日：2013-03-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Scott N. Gatzemeier ,  Wallace E. Fister ,  Adam D. Johnson ,  Benjamin S. Louie

IPC: G11C7/10

CPC classification number: G11C7/10 ,  G11C5/066 ,  G11C29/1201 ,  G11C29/48 ,  G11C2029/2602

Abstract: Methods, memory devices and systems are disclosed. In one embodiment, a non-volatile memory device receives command signals through the same input/output terminals that receive address signals and write data signals and transmit read data signals. The input/output terminals are connected to a multiplexer, which is responsive to a received mode control signal to couple the input/output terminals to either a command bus or an input/output bus. A latch in the memory device latches the command signals when the mode control signal causes the input/output terminals to be coupled to the input/output bus. As a result, the command signals continue to be applied to the command bus. When the mode control signal causes the input/output terminals to be coupled to the input/output bus, write data signals are clocked into the memory device and read data signals are clocked out of the memory device responsive to a received clock signal.