公开(公告)号：US10510773B2

公开(公告)日：2019-12-17

申请号：US15688260

申请日：2017-08-28

Applicant: Micron Technology, Inc.

Inventor： D. V. Nirmal Ramaswamy ,  Adam D. Johnson

IPC: G11C11/22 ,  H01L27/11597 ,  H01L29/78

Abstract: An apparatus comprises field-effect transistor (FET) structures stacked horizontally and vertically in a three-dimensional memory array architecture, gates extending vertically and spaced horizontally between the plurality of FET structures, and a ferroelectric material separating the FET structures and the gates. Individual ferroelectric FETs (FeFETs) are formed at intersections of the FET structures, the gates, and the ferroelectric material. Another apparatus comprises a plurality of bit lines and word lines. Each bit line has at least two sides that are coupled with a ferroelectric material such that each bit line is shared by neighboring gates to form a plurality of FeFETs. A method of operating a memory array comprises applying a combination of voltages to a plurality of word lines and digit lines for a desired operation for a plurality of FeFET memory cells, at least one digit line having the plurality of FeFET memory cells accessible by neighboring gates.

公开(公告)号：US10062432B2

公开(公告)日：2018-08-28

申请号：US14719053

申请日：2015-05-21

Applicant: Micron Technology, Inc.

Inventor： D. V. Nirmal Ramaswamy ,  Gurtej S. Sandhu ,  Lei Bi ,  Adam D. Johnson ,  Brent Keeth ,  Alessandro Calderoni ,  Scott E. Sills

IPC: G11C13/00 ,  G11C11/16

CPC classification number: G11C13/004 ,  G11C11/1673 ,  G11C13/0069 ,  G11C2013/0047 ,  G11C2013/0057

Abstract: The present disclosure includes apparatuses and methods for sensing a resistive memory cell. A number of embodiments include performing a sensing operation on a memory cell to determine a current value associated with the memory cell, applying a programming signal to the memory cell, and determining a data state of the memory cell based on the current value associated with the memory cell before applying the programming signal and a current value associated with the memory cell after applying the programming signal.

公开(公告)号：US20170133076A1

公开(公告)日：2017-05-11

申请号：US15415611

申请日：2017-01-25

Applicant: Micron Technology, Inc.

Inventor： Adam D. Johnson

IPC: G11C11/22

Abstract: Methods for sensing ferroelectric memory devices and apparatuses using the same have been disclosed. One such apparatus includes a ferroelectric memory cell coupled to a data line, a reference capacitance, and a common node coupled between the data line and the reference capacitance. A current mirror circuit is coupled to the data line and the reference capacitance. During a sense operation, the common node is configured to be at a fixed voltage and the current mirror circuit is configured to mirror displacement current from the reference capacitance to the ferroelectric memory cell.

公开(公告)号：US09558803B2

公开(公告)日：2017-01-31

申请号：US14451071

申请日：2014-08-04

Applicant: Micron Technology, Inc.

Inventor： Adam D. Johnson

IPC: G11C11/22

CPC classification number: G11C11/2273

Abstract: Methods for sensing ferroelectric memory devices and apparatuses using the same have been disclosed. One such apparatus includes a ferroelectric memory cell coupled to a data line, a reference capacitance, and a common node coupled between the data line and the reference capacitance. A current mirror circuit is coupled to the data line and the reference capacitance. During a sense operation, the common node is configured to be at a fixed voltage and the current mirror circuit is configured to mirror displacement current from the reference capacitance to the ferroelectric memory cell.

Abstract translation: 已经公开了用于感测铁电存储器件的方法和使用其的装置。 一种这样的装置包括耦合到数据线，参考电容和耦合在数据线和参考电容之间的公共节点的铁电存储单元。 电流镜电路耦合到数据线和参考电容。 在感测操作期间，公共节点被配置为处于固定电压，并且电流镜电路被配置为将来自参考电容的位移电流镜像到铁电存储器单元。

公开(公告)号：US11562782B2

公开(公告)日：2023-01-24

申请号：US16943665

申请日：2020-07-30

Applicant: Micron Technology, Inc.

Inventor： Adam D. Johnson

IPC: G11C11/22

Abstract: Methods for sensing ferroelectric memory devices and apparatuses using the same have been disclosed. One such apparatus includes a ferroelectric memory cell coupled to a data line, a reference capacitance, and a common node coupled between the data line and the reference capacitance. A current mirror circuit is coupled to the data line and the reference capacitance. During a sense operation, the common node is configured to be at a fixed voltage and the current mirror circuit is configured to mirror displacement current from the reference capacitance to the ferroelectric memory cell.

公开(公告)号：US11244733B2

公开(公告)日：2022-02-08

申请号：US16685309

申请日：2019-11-15

Applicant: Micron Technology, Inc.

Inventor： Daniele Vimercati ,  Mark Fischer ,  Adam D. Johnson

IPC: G11C11/34 ,  G11C16/04 ,  G11C16/34 ,  G11C11/56 ,  G11C11/22

Abstract: Methods, systems, and devices for techniques to mitigate disturbances of unselected memory cells in a memory array during an access operation are described. A shunt line may be formed between a plate of a selected memory cell and a digit line of the selected memory cell to couple the plate to the digit line during the access operation. A switching component may be positioned on the shunt line. The switching component may selectively couple the plate to the digit line based on instructions received from a memory controller. By coupling the plate to the digit line during the access operation, voltages resulting on the plate by changes in the voltage level of the digit line may be reduced in magnitude or may be altered in type.

公开(公告)号：US20200090768A1

公开(公告)日：2020-03-19

申请号：US16685309

申请日：2019-11-15

Applicant: Micron Technology, Inc.

Inventor： Daniele Vimercati ,  Mark Fischer ,  Adam D. Johnson

IPC: G11C16/34 ,  G11C11/22 ,  G11C16/04 ,  G11C11/56

Abstract: Methods, systems, and devices for techniques to mitigate disturbances of unselected memory cells in a memory array during an access operation are described. A shunt line may be formed between a plate of a selected memory cell and a digit line of the selected memory cell to couple the plate to the digit line during the access operation. A switching component may be positioned on the shunt line. The switching component may selectively couple the plate to the digit line based on instructions received from a memory controller. By coupling the plate to the digit line during the access operation, voltages resulting on the plate by changes in the voltage level of the digit line may be reduced in magnitude or may be altered in type.

公开(公告)号：US20170098660A1

公开(公告)日：2017-04-06

申请号：US15379933

申请日：2016-12-15

Applicant: Micron Technology, Inc.

Inventor： D.V. Nirmal Ramaswamy ,  Adam D. Johnson

IPC: H01L27/11597 ,  G11C11/22

CPC classification number: H01L27/11597 ,  G11C11/22 ,  G11C11/221 ,  G11C11/223 ,  G11C11/2255 ,  G11C11/2257 ,  H01L29/78391

Abstract: An apparatus comprises field-effect transistor (FET) structures stacked horizontally and vertically in a three-dimensional memory array architecture, gates extending vertically and spaced horizontally between the plurality of FET structures, and a ferroelectric material separating the FET structures and the gates. Individual ferroelectric FETs (FeFETs) are formed at intersections of the FET structures, the gates, and the ferroelectric material. Another apparatus comprises a plurality of bit lines and word lines. Each bit line has at least two sides that are coupled with a ferroelectric material such that each bit line is shared by neighboring gates to form a plurality of FeFETs. A method of operating a memory array comprises applying a combination of voltages to a plurality of word lines and digit lines for a desired operation for a plurality of FeFET memory cells, at least one digit line having the plurality of FeFET memory cells accessible by neighboring gates.

公开(公告)号：US09530794B2

公开(公告)日：2016-12-27

申请号：US14981221

申请日：2015-12-28

Applicant: Micron Technology, Inc.

Inventor： D. V. Nirmal Ramaswamy ,  Adam D. Johnson

IPC: G11C11/22 ,  H01L27/115

CPC classification number: H01L27/11597 ,  G11C11/22 ,  G11C11/221 ,  G11C11/223 ,  G11C11/2255 ,  G11C11/2257 ,  H01L29/78391

Abstract: An apparatus comprises field-effect transistor (FET) structures stacked horizontally and vertically in a three-dimensional memory array architecture, gates extending vertically and spaced horizontally between the plurality of FET structures, and a ferroelectric material separating the FET structures and the gates. Individual ferroelectric FETs (FeFETs) are formed at intersections of the FET structures, the gates, and the ferroelectric material. Another apparatus comprises a plurality of bit lines and word lines. Each bit line has at least two sides that are coupled with a ferroelectric material such that each bit line is shared by neighboring gates to form a plurality of FeFETs. A method of operating a memory array comprises applying a combination of voltages to a plurality of word lines and digit lines for a desired operation for a plurality of FeFET memory cells, at least one digit line having the plurality of FeFET memory cells accessible by neighboring gates.

Abstract translation: 一种装置包括在三维存储阵列结构中水平和垂直堆叠的场效应晶体管（FET）结构，在多个FET结构之间垂直和水平间隔延伸的栅极和分离FET结构和栅极的铁电材料。 在FET结构，栅极和铁电体材料的交叉处形成单个铁电FET（FeFET）。 另一种装置包括多个位线和字线。 每个位线具有与铁电材料耦合的至少两个边，使得每个位线由相邻栅极共享以形成多个FeFET。 操作存储器阵列的方法包括将电压的组合施加到多个字线和数字线以用于多个FeFET存储器单元的期望操作，至少一个数字线具有可由相邻门访问的多个FeFET存储器单元 。

公开(公告)号：US09058875B2

公开(公告)日：2015-06-16

申请号：US13921951

申请日：2013-06-19

Applicant: Micron Technology, Inc.

Inventor： D. V. Nirmal Ramaswamy ,  Gurtej S. Sandhu ,  Lei Bi ,  Adam D. Johnson ,  Brent Keeth ,  Alessandro Calderoni ,  Scott E. Sills

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G11C11/1673 ,  G11C13/0069 ,  G11C2013/0047 ,  G11C2013/0057

Abstract: The present disclosure includes apparatuses and methods for sensing a resistive memory cell. A number of embodiments include performing a sensing operation on a memory cell to determine a current value associated with the memory cell, applying a programming signal to the memory cell, and determining a data state of the memory cell based on the current value associated with the memory cell before applying the programming signal and a current value associated with the memory cell after applying the programming signal.

Abstract translation: 本公开包括用于感测电阻式存储单元的装置和方法。 许多实施例包括对存储器单元执行感测操作以确定与存储器单元相关联的当前值，将编程信号施加到存储器单元，以及基于与存储器单元相关联的当前值来确定存储器单元的数据状态 在施加编程信号之前应用编程信号的存储单元和与存储器单元相关联的当前值。