公开(公告)号：US20250103214A1

公开(公告)日：2025-03-27

申请号：US18790233

申请日：2024-07-31

Applicant: Micron Technology, Inc.

Inventor： Phong S. Nguyen ,  Dung Viet Nguyen ,  James Fitzpatrick ,  Steven Raymond Brown

IPC: G06F3/06

Abstract: Described are systems and methods for dynamically configurable data modulation in memory systems. An example memory sub-system comprises a controller managing one or more memory devices. The controller is configured to perform operations, comprising: receiving a unit of data to be stored on the memory device; identifying a set of parameter values characterizing a target location of the unit of data on the memory device; determining a modulation code corresponding to the set of parameter values; modulating the unit of data by a modulation operation identified by the modulation code; and storing, on the memory device, the modulated unit of data.

公开(公告)号：US20230176789A1

公开(公告)日：2023-06-08

申请号：US18103857

申请日：2023-01-31

Applicant: Micron Technology, Inc.

Inventor： Ting Luo ,  Xiangang Luo ,  Jianmin Huang ,  Phong S. Nguyen

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679

Abstract: A method includes receiving a command to write data to a memory device and writing the data to a first memory tier of the memory device. The first memory tier of the memory device is a dynamic memory tier that utilizes single level cells (SLCs), multi-level cells (MLCs), and triple level cells (TLCs). The method further includes migrating the data from the first memory tier of the memory device to a second memory tier of the memory device. The second memory tier of the memory device is a static memory tier that utilizes quad level cells (QLCs).

公开(公告)号：US20230043733A1

公开(公告)日：2023-02-09

申请号：US17395695

申请日：2021-08-06

Applicant: Micron Technology, Inc.

Inventor： Ting Luo ,  Xiangang Luo ,  Jianmin Huang ,  Phong S. Nguyen

IPC: G06F3/06

Abstract: A method includes receiving a command to write data to a memory device and writing the data to a first memory tier of the memory device. The first memory tier of the memory device is a dynamic memory tier that utilizes single level cells (SLCs), multi-level cells (MLCs), and triple level cells (TLCs). The method further includes migrating the data from the first memory tier of the memory device to a second memory tier of the memory device. The second memory tier of the memory device is a static memory tier that utilizes quad level cells (QLCs).

公开(公告)号：US20240330105A1

公开(公告)日：2024-10-03

申请号：US18615592

申请日：2024-03-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Phong S. Nguyen ,  Dung Viet Nguyen ,  James Fitzpatrick ,  Sivagnanam Parthasarathy ,  Zhengang Chen

IPC: G06F11/10

CPC classification number: G06F11/1004 ,  G06F11/1068

Abstract: Input data is received for storage by a system. The input data is encoded using a low-density parity-check (LDPC) matrix to generate encoded data, wherein the LDPC matrix is selected from a plurality of LDPC matrices, each of the plurality of LDPC matrices having a common size and a unique degree distribution. The encoded data is then stored on a memory device of the system.

公开(公告)号：US11829650B2

公开(公告)日：2023-11-28

申请号：US18103857

申请日：2023-01-31

Applicant: Micron Technology, Inc.

Inventor： Ting Luo ,  Xiangang Luo ,  Jianmin Huang ,  Phong S. Nguyen

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679

Abstract: A method includes receiving a command to write data to a memory device and writing the data to a first memory tier of the memory device. The first memory tier of the memory device is a dynamic memory tier that utilizes single level cells (SLCs), multi-level cells (MLCs), and triple level cells (TLCs). The method further includes migrating the data from the first memory tier of the memory device to a second memory tier of the memory device. The second memory tier of the memory device is a static memory tier that utilizes quad level cells (QLCs).

公开(公告)号：US20250103213A1

公开(公告)日：2025-03-27

申请号：US18790132

申请日：2024-07-31

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Phong S. Nguyen ,  Dung Viet Nguyen ,  James Fitzpatrick ,  Sivagnanam Parthasarathy

IPC: G06F3/06

Abstract: Described are systems and methods for adaptable data modulation. An example memory sub-system comprises a controller managing one or more memory devices. The controller is configured to perform operations, comprising: receiving a unit of data to be written to the memory device; splitting the unit of data into a plurality of segments; modulating each segment of the unit of data by a modulation operation using a modulation mask derived from a corresponding seed value; and generating a modulated unit of data comprising a plurality of modulated segments and a plurality of corresponding seed identifiers, wherein each seed identifier identifies a seed value that has been used for modulating a respective segment of the unit of data.

公开(公告)号：US11593032B1

公开(公告)日：2023-02-28

申请号：US17395695

申请日：2021-08-06

Applicant: Micron Technology, Inc.

Inventor： Ting Luo ,  Xiangang Luo ,  Jianmin Huang ,  Phong S. Nguyen

IPC: G06F3/06

Abstract: A method includes receiving a command to write data to a memory device and writing the data to a first memory tier of the memory device. The first memory tier of the memory device is a dynamic memory tier that utilizes single level cells (SLCs), multi-level cells (MLCs), and triple level cells (TLCs). The method further includes migrating the data from the first memory tier of the memory device to a second memory tier of the memory device. The second memory tier of the memory device is a static memory tier that utilizes quad level cells (QLCs).

公开(公告)号：US20250110658A1

公开(公告)日：2025-04-03

申请号：US18781696

申请日：2024-07-23

Applicant: Micron Technology, Inc.

Inventor： Mariano Eduardo Burich ,  Sivagnanam Parthasarathy ,  Mustafa N. Kaynak ,  Eyal En Gad ,  Phong S. Nguyen ,  Dung Viet Nguyen

IPC: G06F3/06

Abstract: A soft input is obtained from a sense word corresponding to encoded host data read from the memory device and decoded using a parity-check matrix. A match array is maintained. Each iteration of an error correcting code operation a number of unsatisfied check nodes of a respective bit of the sense word is calculated for each bit of the sense word. A bit flip threshold from a threshold data structure is obtained based on a current iteration of the error correcting code operation, a soft bit associated with the respective bit, and a match bit associated with the respective bit. The respective bit is flipped based on the number of unsatisfied check nodes satisfying the bit flip threshold.

公开(公告)号：US20250103238A1

公开(公告)日：2025-03-27

申请号：US18781970

申请日：2024-07-23

Applicant: Micron Technology, Inc.

Inventor： Phong S. Nguyen ,  Dung Viet Nguyen

IPC: G06F3/06

Abstract: Described are systems and methods for selecting a modulation code permutation for data modulation in a memory system. An example memory sub-system comprises a controller managing one or more memory devices. The controller is configured to perform operations including: receiving data to be written to the memory device; selecting, from a set of modulation code permutations for modifying data to be written to the memory device, a modulation code permutation; determining that a cost metric value corresponding to storing data modified by the modulation code permutation on the memory device satisfies a target condition; generating, using the modulation code permutation, modulated data from the data to be written; and storing, on the memory device, the modulated data.

公开(公告)号：US20250103230A1

公开(公告)日：2025-03-27

申请号：US18781692

申请日：2024-07-23

Applicant: Micron Technology, Inc.

Inventor： Dung Viet Nguyen ,  Phong S. Nguyen ,  James Fitzpatrick

IPC: G06F3/06

Abstract: Host data to be programmed to a plurality of memory cells associated with a wordline of a memory device is received from a host system. The host data into a plurality of partitions is divided. Each of the plurality of partitions is divided into a respective plurality of sub-partitions. One or more modulation mappings to be applied to the plurality of sub-partitions are determined based on the host data of the plurality of partitions. Host data of each sub-partition of the plurality of sub-partitions is modified based on the one or more modulation mappings. The modified host data of each sub-partition is written to the plurality of memory cells associated with the wordline.