公开(公告)号：US20250158715A1

公开(公告)日：2025-05-15

申请号：US18934961

申请日：2024-11-01

Applicant: Micron Technology, Inc.

Inventor： Saideep Tiku ,  Poorna Kale ,  Febin Sunny

IPC: H04B10/27 ,  H04Q11/00

Abstract: Systems, methods, and apparatuses related to channel management are described herein. An optical communication system can comprise an optical source configured to send optical signals, a meta-waveguide having a limited quantity of channels, the meta waveguide coupled to the optical source and configured to transport the optical signals, and a controller coupled to the optical source and the meta-waveguide, the controller configured to determine a type of data to be sent via the meta-waveguide, cause optical signals indicative of the data to be sent through at least one of the channels, and cause a gap comprising at least one unutilized channel to be reserved between the at least one channel and another utilized channel depending on the type of data.

公开(公告)号：US20250125978A1

公开(公告)日：2025-04-17

申请号：US18785825

申请日：2024-07-26

Applicant: Micron Technology, Inc.

Inventor： Saideep Tiku ,  Febin Sunny ,  Poorna Kale

IPC: H04L9/32 ,  H04L9/40

Abstract: Apparatuses, non-transitory machine-readable media, and methods associated with passive photonic physically unclonable functionality for securing an automotive powertrain control area network are described herein. One apparatus includes a first network node communicatively connected via photonic interconnections to a second network node, the first network node has a passive photonic encryption unit for encrypting data packets by utilizing a microring resonator (MR) having at least one fabrication process variation (FPV) that is unique from the MRs of the other nodes, a decryption unit having a look up table (LUT) including at least one node identifier and containing information about at least one FPV of one of the network nodes to decrypt data packets, and a processing unit that processes the contents of the decrypted data packets.

公开(公告)号：US12277491B2

公开(公告)日：2025-04-15

申请号：US17316496

申请日：2021-05-10

Applicant: Micron Technology, Inc.

Inventor： Poorna Kale ,  Saideep Tiku

IPC: G06N3/063 ,  G06F12/123 ,  G06F21/14 ,  G06F21/60 ,  G06F21/62 ,  G06N3/04 ,  G06N3/045 ,  G06N3/0455 ,  G06N3/08 ,  G11C16/08

Abstract: Apparatuses and methods can be related to encoding traffic between a host and a deep learning accelerator (DLA). Traffic between a host can be encoded utilizing an autoencoder. Encoding traffic between a host and a DLA changes the bandwidth of the traffic. Changing the bandwidth of the traffic prevents the correlation between the bandwidth and the input from which the traffic is generated.

公开(公告)号：US12246736B2

公开(公告)日：2025-03-11

申请号：US16942438

申请日：2020-07-29

Applicant: Micron Technology, Inc.

Inventor： Poorna Kale ,  Amit Gattani

IPC: B60W50/04 ,  G06F13/42 ,  G06F18/214 ,  G06F18/24 ,  G06N3/08

Abstract: Systems, methods and apparatus of integrated image sensing devices. In one example, a system includes a sensor that generates data. A memory device stores the generated data, and further stores a first portion of an artificial neural network (ANN). A host interface of the system is configured to communicate with a host system that stores a second portion of the ANN. The memory device can be stacked with the sensor. The memory device includes an inference engine configured to generate inference results using the stored data as input to the first portion of the ANN. The host interface is further configured to send the inference results to the host system for processing by the host system using the second portion of the ANN.

公开(公告)号：US20250041663A1

公开(公告)日：2025-02-06

申请号：US18753758

申请日：2024-06-25

Applicant: Micron Technology, Inc.

Inventor： Shashank Bangalore Lakshman ,  Pavana Prakash ,  Poorna Kale

IPC: A63B24/00 ,  G06F18/20 ,  G06N20/20

Abstract: Systems, methods, devices, and apparatus are provided for device training at a determined quantization. For instance, a device can include a battery, a communication node, a sensor configured to collect user fitness data, and a processor coupled to the battery, the communication node, and the sensor. The processor can be configured to monitor a power state of the battery, determine a usage pattern of the electronic device and determine a quantization at which to train a machine learning model for analyzing the user fitness data based on the power state and the usage pattern. In addition, the processor can be configured to train the machine learning model at the determined quantization using the user fitness data and transmit the determined quantization and an update to the trained machine learning model via the communication node without transmitting the user fitness data.

公开(公告)号：US12217159B2

公开(公告)日：2025-02-04

申请号：US16987123

申请日：2020-08-06

Applicant: Micron Technology, Inc.

Inventor： Poorna Kale

IPC: G06N3/063 ,  G06F9/30 ,  G06F9/50 ,  G06F17/16 ,  G06F30/27 ,  G06N3/08

Abstract: Systems, devices, and methods related to a Deep Learning Accelerator and memory are described. For example, an integrated circuit device may be configured to execute instructions with matrix operands and configured with random access memory (RAM) to store parameters of an artificial neural network (ANN). The device can generate random bit errors to simulate compromised or corrupted memory cells in a portion of the RAM accessed during computations of a first ANN output. A second ANN output is generated with the random bit errors applied to the data retrieved from the portion of the RAM. Based on a difference between the first and second ANN outputs, the device may adjust the ANN computation to reduce sensitivity to compromised or corrupted memory cells in the portion of the RAM. For example, the sensitivity reduction may be performed through ANN training using machine learning.

公开(公告)号：US12175126B2

公开(公告)日：2024-12-24

申请号：US17652412

申请日：2022-02-24

Applicant: Micron Technology, Inc.

Inventor： Poorna Kale

IPC: G06F3/06

Abstract: Methods, systems, and devices for techniques to season memory cells are described. A memory device may receive a command to season the memory device from a device configured to season the memory device or from a host device. Based on receiving the command, the memory device may identify a quantity of cycles to season the memory device based on receiving the command. In one case, the memory device may identify the quantity of cycles based on the command including an indication of the quantity of cycles used to season the memory device. In another case, the memory device may identify the quantity of cycles based on the command including one or more parameters associated with operating the memory device. In either case, the memory device may execute the quantity of cycles and indicate a completion of seasoning the memory device based on executing the quantity of cycles.

公开(公告)号：US12149851B2

公开(公告)日：2024-11-19

申请号：US17940937

申请日：2022-09-08

Applicant: Micron Technology, Inc.

Inventor： Poorna Kale

IPC: H04N25/771 ,  G11C7/10 ,  H04N25/709 ,  H04N25/74 ,  H04N25/79

Abstract: An integrated circuit device having a memory cell array with first layers of memory cells configured for operations of multiplication and accumulation. Each pair of closest layers among the first layers are configured to be separate by at least one layer in second layers of memory cells, where access to, or usages of, the second layers can be restricted or limited to prevent activities in the second layers from corrupting the weight programming in the first layers.

公开(公告)号：US20240370175A1

公开(公告)日：2024-11-07

申请号：US18651480

申请日：2024-04-30

Applicant: Micron Technology, Inc.

Inventor： Saideep Tiku ,  Febin Sunny ,  Poorna Kale

IPC: G06F3/06

Abstract: A controller of a high bandwidth interconnect between a memory sub-system and a processor sub-system configured to regulate access to memories in the memory sub-system. Using data indicative of memory access activities in a plurality of memories during a first time period, the controller can evaluate thermal stresses in memories during a first time period, group memories into memory batches, and schedule and imposing, idle times for the batches in a second time period following the first time period. After receiving requests to access the plurality of memories during the second time period, the controller can throttle communications of the requests to memory controllers and/or to the memory sub-system to enforce the idle times pre-scheduled for the memory batches in the second time period.

公开(公告)号：US20240369771A1

公开(公告)日：2024-11-07

申请号：US18651521

申请日：2024-04-30

Applicant: Micron Technology, Inc.

Inventor： Febin Sunny ,  Saideep Tiku ,  Poorna Kale

IPC: G02B6/293 ,  G02B6/122

Abstract: A computing system having a plurality of memory sub-systems and a central host. Each of the memory sub-systems has a first optical interface module. The central host has second optical interface module. The central host and the plurality of memory sub-systems are connected through a plurality of optical fibers in a ring topology network of connections. The central host can partition computations of an application into multiple parts executable in a pipeline to perform the computations of the application. The central host can write data specifying computations of the parts into the memory sub-systems and instruct the memory sub-systems to perform pipelined processing of the parts via communications over the ring topology network of connections.