公开(公告)号：US11769076B2

公开(公告)日：2023-09-26

申请号：US16601386

申请日：2019-10-14

Applicant: Micron Technology, Inc.

Inventor： Amit Gattani ,  Poorna Kale

IPC: G06N20/00 ,  G06F13/16 ,  G06F3/06 ,  G06N3/08

CPC classification number: G06N20/00 ,  G06F3/061 ,  G06F3/0659 ,  G06F13/1668 ,  G06N3/08

Abstract: A memory component includes a memory region to store a machine learning model and input data and another memory region to store host data from a host system. A controller can be coupled to the memory component and can include in-memory logic to perform a machine learning operation by applying the machine learning model to the input data to generate an output data. A bus can receive additional data from the host system and a decoder can receive the additional data from the bus and can transmit the additional data to the other memory region or the in-memory logic of the controller based on a characteristic of the additional data.

公开(公告)号：US20220383917A1

公开(公告)日：2022-12-01

申请号：US17887851

申请日：2022-08-15

Applicant: Micron Technology, Inc.

Inventor： Poorna Kale ,  Amit Gattani

IPC: G11C7/10 ,  G06N3/08 ,  G06F7/544 ,  G06F17/16

Abstract: A dual-port, dual function memory device can be configured to perform operations on data written to the memory device using artificial intelligence (AI) circuitry, such as a neuromorphic array and/or a deep learning accelerator (DLA), of the memory device. The memory device can include a port dedicated for communication between the AI circuitry and a host device and another port dedicated for communication between a memory array of the memory device and a host device. Performing operations, such as image processing operations, using AI circuitry of a memory device can reduce data transfers, reduce resource consumption, and offload workloads from a host device.

公开(公告)号：US20220036157A1

公开(公告)日：2022-02-03

申请号：US16942341

申请日：2020-07-29

Applicant: Micron Technology, Inc.

Inventor： Poorna Kale ,  Amit Gattani

IPC: G06N3/04 ,  G06N3/063

Abstract: Methods, systems, and apparatus related to dynamic distribution of an artificial neural network among multiple processing nodes based on real-time monitoring of a processing load on each node. In one approach, a server acts as an intelligent artificial intelligence (AI) gateway. The server receives data regarding a respective operating status for each of monitored processing devices. The monitored processing devices perform processing for an artificial neural network (ANN). The monitored processing devices each perform processing for a portion of the neurons in the ANN. The portions are distributed in response to monitoring the processing load on each processing device (e.g., to better utilize processing power across all of the processing devices).

公开(公告)号：US11729318B2

公开(公告)日：2023-08-15

申请号：US16951971

申请日：2020-11-18

Applicant: Micron Technology, Inc.

Inventor： Poorna Kale ,  Richard C. Murphy ,  Amit Gattani

IPC: G06F13/42 ,  H04N1/41 ,  H04N23/80 ,  H04N23/60 ,  H04N1/00 ,  H04N1/60 ,  G06F13/16 ,  H04N1/64

CPC classification number: H04N1/00193 ,  G06F13/1668 ,  G06F13/4234 ,  G06F13/4282 ,  H04N1/41 ,  H04N1/6016 ,  H04N1/64 ,  H04N23/665 ,  H04N23/80

Abstract: A memory device can be configured to direct communication of data from an image sensor to the memory device and/or image signal processing circuitry coupled thereto. The memory device can be configured to receive first signaling indicative of first data from an image sensor via a first port and provide the first signaling from the memory device to image signal processing (ISP) circuitry via a second port. The memory device can be configured to receiving, by the memory device, second signaling indicative of second data from the image sensor while the ISP circuitry operates on the first data. An image processing operation can be performed using logic circuitry of the memory device. Directing communication of data using the memory device can reduce data transfers, reduce resource consumption of an imaging system, and offload workloads from a host device and/or a host processing device, for example.

公开(公告)号：US11681909B2

公开(公告)日：2023-06-20

申请号：US16601376

申请日：2019-10-14

Applicant: Micron Technology, Inc.

Inventor： Poorna Kale ,  Amit Gattani

IPC: G05B13/02 ,  G05G7/00 ,  G06G1/00 ,  G06N3/08 ,  G06N3/04 ,  G06F13/16

CPC classification number: G06N3/08 ,  G06F13/1668 ,  G06N3/04

Abstract: Memory cells can include a memory region to store a machine learning model and input data and another memory region to store host data from a host system. An in-memory logic can be coupled to the plurality of memory cells and can perform a machine learning operation by applying the machine learning model to the input data to generate an output data. A bus can receive additional host data from the host system and can provide the additional host data to the memory component for the other memory region of the plurality of memory cells. An additional bus can receive machine learning data from the host system and can provide the machine learning data to the memory component for the in-memory logic that is to perform the machine learning operation.

公开(公告)号：US20220180907A1

公开(公告)日：2022-06-09

申请号：US17116759

申请日：2020-12-09

Applicant: Micron Technology, Inc.

Inventor： Poorna Kale ,  Amit Gattani

IPC: G11C7/10 ,  G06F7/544 ,  G06F17/16 ,  G06N3/08

Abstract: A dual-port, dual function memory device can be configured to perform operations on data written to the memory device using artificial intelligence (AI) circuitry, such as a neuromorphic array and/or a deep learning accelerator (DLA), of the memory device. The memory device can include a port dedicated for communication between the AI circuitry and a host device and another port dedicated for communication between a memory array of the memory device and a host device. Performing operations, such as image processing operations, using AI circuitry of a memory device can reduce data transfers, reduce resource consumption, and offload workloads from a host device.

公开(公告)号：US20210127090A1

公开(公告)日：2021-04-29

申请号：US17080619

申请日：2020-10-26

Applicant: Micron Technology, Inc.

Inventor： Poorna Kale ,  Amit Gattani

IPC: H04N7/18 ,  G06N5/04 ,  G06N3/04 ,  G06F13/42 ,  G06F13/16 ,  G06F3/06 ,  H04N5/247 ,  H04N5/76 ,  G05D1/02 ,  G05D1/00

Abstract: Systems, methods, and apparatus for intelligent image sensing devices. In one example, a host interface of a sensing device receives sensor data from a host system. The sensing device stores the sensor data in response to a write command received from the host system. The sensing device also stores data from an image stream generated by an image sensor(s) included in the sensing device. An inference engine of the sensing device generates inference results using both the image stream and the sensor data as input. The sensing device stores the inference results in a non-volatile memory for access by the host system. In response to receiving a read command from the host system, the sensing device provides the inference results to the host system.

公开(公告)号：US20210110251A1

公开(公告)日：2021-04-15

申请号：US16601381

申请日：2019-10-14

Applicant: Micron Technology, Inc.

Inventor： Amit Gattani ,  Poorna Kale

IPC: G06N3/08 ,  G06F13/16 ,  G06N3/04

Abstract: A memory component can include memory cells where a first region of the memory cells is to store a machine learning model and a second region of the memory cells is to store input data and output data of a machine learning operation. A controller can be coupled to the memory component with one more internal buses to perform the machine learning operation by applying the machine learning model to the input data to generate the output data.

公开(公告)号：US12246736B2

公开(公告)日：2025-03-11

申请号：US16942438

申请日：2020-07-29

Applicant: Micron Technology, Inc.

Inventor： Poorna Kale ,  Amit Gattani

IPC: B60W50/04 ,  G06F13/42 ,  G06F18/214 ,  G06F18/24 ,  G06N3/08

Abstract: Systems, methods and apparatus of integrated image sensing devices. In one example, a system includes a sensor that generates data. A memory device stores the generated data, and further stores a first portion of an artificial neural network (ANN). A host interface of the system is configured to communicate with a host system that stores a second portion of the ANN. The memory device can be stacked with the sensor. The memory device includes an inference engine configured to generate inference results using the stored data as input to the first portion of the ANN. The host interface is further configured to send the inference results to the host system for processing by the host system using the second portion of the ANN.

公开(公告)号：US11830574B2

公开(公告)日：2023-11-28

申请号：US17887851

申请日：2022-08-15

Applicant: Micron Technology, Inc.

Inventor： Poorna Kale ,  Amit Gattani

IPC: G11C7/10 ,  G06N3/08 ,  G06F7/544 ,  G06F17/16

CPC classification number: G11C7/1075 ,  G06F7/5443 ,  G06F17/16 ,  G06N3/08 ,  G11C7/1084 ,  G11C7/1096

Abstract: A dual-port, dual function memory device can be configured to perform operations on data written to the memory device using artificial intelligence (AI) circuitry, such as a neuromorphic array and/or a deep learning accelerator (DLA), of the memory device. The memory device can include a port dedicated for communication between the AI circuitry and a host device and another port dedicated for communication between a memory array of the memory device and a host device. Performing operations, such as image processing operations, using AI circuitry of a memory device can reduce data transfers, reduce resource consumption, and offload workloads from a host device.