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公开(公告)号：US11870616B2
公开(公告)日：2024-01-09
申请号：US17157815
申请日：2021-01-25
发明人： Stefan Dietrich , Natalija Jovanovic , Ronny Schneider , Martin Brox , Thomas Hein , Michael Dieter Richter
CPC分类号： H04L25/4917 , H04L1/0003
摘要： Methods, systems, and devices for postamble for multi-level signal modulation are described. One or more channels of a bus may be driven with a multi-level signal having at least two (2) distinct signal levels. After driving the bus with the multi-level signal, at least one (1) of the channels may be terminated. In some examples, the channel may be terminated to a relatively high signal level. Before termination, the channel may be driven with a postamble having an intermediate signal level. Driving the channel to an intermediate signal level before terminating the channel (e.g., to a high signal level) may avoid maximum transitions of the signal. For example, transitions between a lowest potential signal level and the high signal level (e.g., the termination level) may be avoided.
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公开(公告)号：US11621033B2
公开(公告)日：2023-04-04
申请号：US17145066
申请日：2021-01-08
发明人： Martin Brox , Thomas Hein , Stefan Dietrich , Natalija Jovanovic , Ronny Schneider , Michael Dieter Richter
IPC分类号： G11C11/4076 , H01L27/00 , H04L27/00 , G11C7/10 , G11C11/4093
摘要： Methods, systems, and devices for techniques for low power operation are described. A device may be configurable to operate in a first mode and a second mode, where the first mode may include transmitting using a first modulation scheme having two logic levels and the second mode may include transmitting using a second modulation scheme having three or more (e.g., four) logic levels. The device may identify a data symbol for transmission and select, from the first mode and the second mode, the first modulation scheme for the transmission. In some example, the device may determine which of the two modes to select based on a value stored at a mode register. Here, the value stored by the mode register may indicate to utilize the first modulation scheme associated with the first mode. Thus, the device may transmit the data symbol by a signal modulated by the first modulation scheme.
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公开(公告)号：US11281529B2
公开(公告)日：2022-03-22
申请号：US17170462
申请日：2021-02-08
摘要： Methods, systems, and devices related to error detection code generation techniques are described. A memory device may identify a first set of bits for transmission to a host device and calculate an error detection code associated with the first set of bits. Prior to transmitting the first set of bits, the memory device may modify one or more bits of the first set of bits to generate a second set of bits for transmission from the memory device to the host device. The memory device may modify one or more bits of the first error detection code to generate a second error detection code based on a parity of the modified one or more bits of the first set of bits. The memory device may transmit the second set of bits and the second error detection code to the host device.
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公开(公告)号：US20230188248A1
公开(公告)日：2023-06-15
申请号：US18108065
申请日：2023-02-10
发明人： Stefan Dietrich , Thomas Hein , Natalija Jovanovic , Ronny Schneider , Michael Dieter Richter , Martin Brox
IPC分类号： H04L1/00
CPC分类号： H04L1/0003
摘要： Methods, systems, and devices for data inversion techniques are described to enable a memory device to transmit or receive a multi-symbol signal that includes more than two (2) physical levels. Some portions of some multi-symbol signals may be inverted. A transmitting device may determine to invert one or more data symbols based on one or more parameters. A receiving device may determine that one or more data symbols are inverted and may re-invert the one or more data symbols (e.g., to an original value). When receiving or transmitting a multi-symbol signal, a device may invert or re-invert a data symbol by changing a value of one bit of the data symbol. Additionally or alternatively, a device may invert or re-invert a data symbol of a multi-symbol signal by inverting a physical level of the signal across an axis located between or associated with one or more physical levels.
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公开(公告)号：US11675656B2
公开(公告)日：2023-06-13
申请号：US17675766
申请日：2022-02-18
CPC分类号： G06F11/1004
摘要： Methods, systems, and devices related to error detection code generation techniques are described. A memory device may identify a first set of bits for transmission to a host device and calculate an error detection code associated with the first set of bits. Prior to transmitting the first set of bits, the memory device may modify one or more bits of the first set of bits to generate a second set of bits for transmission from the memory device to the host device. The memory device may modify one or more bits of the first error detection code to generate a second error detection code based on a parity of the modified one or more bits of the first set of bits. The memory device may transmit the second set of bits and the second error detection code to the host device.
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公开(公告)号：US20210255918A1
公开(公告)日：2021-08-19
申请号：US17170462
申请日：2021-02-08
IPC分类号： G06F11/10
摘要： Methods, systems, and devices related to error detection code generation techniques are described. A memory device may identify a first set of bits for transmission to a host device and calculate an error detection code associated with the first set of bits. Prior to transmitting the first set of bits, the memory device may modify one or more bits of the first set of bits to generate a second set of bits for transmission from the memory device to the host device. The memory device may modify one or more bits of the first error detection code to generate a second error detection code based on a parity of the modified one or more bits of the first set of bits. The memory device may transmit the second set of bits and the second error detection code to the host device.
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公开(公告)号：US20210224149A1
公开(公告)日：2021-07-22
申请号：US17150480
申请日：2021-01-15
发明人： Stefan Dietrich , Martin Brox , Michael Dieter Richter , Thomas Hein , Ronny Schneider , Natalija Jovanovic
IPC分类号： G06F11/10
摘要： Methods, systems, and devices for bit and signal level mapping are described to enable a memory device to transmit or receive a multi-symbol signal that includes more than two (2) physical levels. Some cyclic redundancy check (CRC) calculations may generate one or more bits of CRC output per symbol of an associated signal and the output may be transmitted via a multi-symbol signal by converting one or more CRC output bit to a physical level of the signal. The conversion, or mapping, process may be performed such that the physical levels of the signal avoid a transition between a highest physical level and lowest physical level. For example, a modulation scheme or mapping process may be configured to map different values of CRC output bits to different physical levels, where the different physical levels are separated by one other physical level associated with the signal or the modulation scheme.
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公开(公告)号：US20210217458A1
公开(公告)日：2021-07-15
申请号：US17145066
申请日：2021-01-08
发明人： Martin Brox , Thomas Hein , Stefan Dietrich , Natalija Jovanovic , Ronny Schneider , Michael Dieter Richter
IPC分类号： G11C11/4076 , H04L27/00
摘要： Methods, systems, and devices for techniques for low power operation are described. A device may be configurable to operate in a first mode and a second mode, where the first mode may include transmitting using a first modulation scheme having two logic levels and the second mode may include transmitting using a second modulation scheme having three or more (e.g., four) logic levels. The device may identify a data symbol for transmission and select, from the first mode and the second mode, the first modulation scheme for the transmission. In some example, the device may determine which of the two modes to select based on a value stored at a mode register. Here, the value stored by the mode register may indicate to utilize the first modulation scheme associated with the first mode. Thus, the device may transmit the data symbol by a signal modulated by the first modulation scheme.
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公开(公告)号：US10171106B2
公开(公告)日：2019-01-01
申请号：US15606194
申请日：2017-05-26
发明人： Stefan Dietrich
摘要： An integrated circuit includes first and second double data rate (DDR) shift registers. A multiplexor outputs a serialized data burst by selecting between a first output stream of the first DDR shift register and a second output stream of the second DDR shift register based upon a received selector signal. The selector signal is derived from clock doubling circuitry that provides a frequency that is twice a frequency of a first clock driving the first DDR shift register.
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公开(公告)号：US12015476B2
公开(公告)日：2024-06-18
申请号：US18108065
申请日：2023-02-10
发明人： Stefan Dietrich , Thomas Hein , Natalija Jovanovic , Ronny Schneider , Michael Dieter Richter , Martin Brox
IPC分类号： H04L1/00
CPC分类号： H04L1/0003
摘要： Methods, systems, and devices for data inversion techniques are described to enable a memory device to transmit or receive a multi-symbol signal that includes more than two (2) physical levels. Some portions of some multi-symbol signals may be inverted. A transmitting device may determine to invert one or more data symbols based on one or more parameters. A receiving device may determine that one or more data symbols are inverted and may re-invert the one or more data symbols (e.g., to an original value). When receiving or transmitting a multi-symbol signal, a device may invert or re-invert a data symbol by changing a value of one bit of the data symbol. Additionally or alternatively, a device may invert or re-invert a data symbol of a multi-symbol signal by inverting a physical level of the signal across an axis located between or associated with one or more physical levels.
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