公开(公告)号：US20240311231A1

公开(公告)日：2024-09-19

申请号：US18525395

申请日：2023-11-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Sujeet Ayyapureddi ,  Wesley W. Borie ,  Dennis G. Montierth ,  Garth N. Grubb ,  Mow Yiak Goh ,  Anthony M. Geidl

IPC: G06F11/10 ,  G06F12/02

CPC classification number: G06F11/10 ,  G06F12/0292 ,  G06F2212/1032

Abstract: An exemplary host includes a data mapping decoder configured to decode a swizzle mapping signal received from a memory module to provide a data mapping setting, a data input/output circuit configured to receive a plurality of data bits from the memory module via a data bus, and a data adjustment circuit configured to re-arrange an order of the plurality of data bits based on the data mapping setting to provide a plurality of adjusted data bits.

公开(公告)号：US20240311238A1

公开(公告)日：2024-09-19

申请号：US18525354

申请日：2023-11-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Wesley W. Borie ,  Dennis G. Montierth ,  Garth N. Grubb ,  Mow Yiak Goh ,  Anthony M. Geidl

IPC: G06F11/10 ,  G06F11/16 ,  G11C8/08 ,  G11C17/16

CPC classification number: G06F11/1068 ,  G06F11/1654 ,  G11C8/08 ,  G11C17/16

Abstract: An exemplary memory includes a first sub-wordline (SWL) driver configured to provide first data from a memory cell array, a second SWL driver configured to provide second data from a memory cell array, and an input/output (I/O) circuit configured to receive the first data and the second data from the first and second SWL drivers, respectively. The I/O circuit including a data terminal mapping circuit configured to selectively route the first data and the second data to different respective data terminal based on a data terminal mapping setting.