公开(公告)号：US20210319826A1

公开(公告)日：2021-10-14

申请号：US16844182

申请日：2020-04-09

Applicant: MICRON TECHNOLOGY, INC.

Inventor： William Chad Waldrop ,  Daniel B. Penney

IPC: G11C11/4076 ,  H04L25/03 ,  G11C11/4096 ,  G11C11/4093

Abstract: Systems and methods are provided that include an interamble data strobe (DQS) counter configured to count cycles between write operations. The interamble DQS counter includes a decision feedback equalizer (DFE) reset mask circuit configured to generate a DFE reset enable signal and a DFE reset timing generator configured to generate timing signals for the DFE reset. The systems and methods also include a DFE reset generator configured to receive the DFE reset enable signal and the timing signals from the interamble DQS counter, to use the DFE reset enable signal and the timing signals to generate DFE reset signals for a plurality of DQS phases; and to transmit the DFE reset signals to the plurality of DQS phases.

公开(公告)号：US20240347102A1

公开(公告)日：2024-10-17

申请号：US18542581

申请日：2023-12-15

Applicant: Micron Technology, Inc.

Inventor： William Chad Waldrop ,  Ki-Jun Nam ,  Won Joo Yun ,  Shingo Mitsubori

IPC: G11C11/4093

CPC classification number: G11C11/4093

Abstract: Systems and methods are provided for a memory device that includes a decision feedback equalizer (DFE) reset generator configured to transmit a DFE reset signal to reset taps of a DFE. The memory device also includes an input buffer. The input buffer includes a data branch configured to output data from the input buffer for use downstream in the memory device. The input buffer also includes a DFE reset branch configured to reset the taps for the DFE based on the DFE reset signal. Moreover, resetting the taps using the DFE reset branch does not reset output data of the data branch.

公开(公告)号：US20220262413A1

公开(公告)日：2022-08-18

申请号：US17178475

申请日：2021-02-18

Applicant: Micron Technology, Inc.

Inventor： William Chad Waldrop ,  Gary L. Howe

IPC: G11C7/10 ,  G11C11/4076 ,  G11C11/4093

Abstract: Systems and methods described herein provide decision feedback equalizer (DFE) circuitry that includes one or more phases. The one or more phases receive bit feedback at respective inputs of the phases. The DFE circuitry also may include variable reset circuitry. The variable reset circuitry may reset voltages of the bit feedback at inputs of each of the phases. The variable reset circuitry is configured to change its reset frequency between resets.

公开(公告)号：US11145353B1

公开(公告)日：2021-10-12

申请号：US16844182

申请日：2020-04-09

Applicant: MICRON TECHNOLOGY, INC.

Inventor： William Chad Waldrop ,  Daniel B. Penney

IPC: G11C7/10 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096 ,  H04L25/03

Abstract: Systems and methods are provided that include an interamble data strobe (DQS) counter configured to count cycles between write operations. The interamble DQS counter includes a decision feedback equalizer (DFE) reset mask circuit configured to generate a DFE reset enable signal and a DFE reset timing generator configured to generate timing signals for the DFE reset. The systems and methods also include a DFE reset generator configured to receive the DFE reset enable signal and the timing signals from the interamble DQS counter, to use the DFE reset enable signal and the timing signals to generate DFE reset signals for a plurality of DQS phases; and to transmit the DFE reset signals to the plurality of DQS phases.

公开(公告)号：US12223999B2

公开(公告)日：2025-02-11

申请号：US17853517

申请日：2022-06-29

Applicant: Micron Technology, Inc.

Inventor： William Chad Waldrop ,  David R. Brown ,  Guy S. Perry, IV

IPC: G11C11/4093

Abstract: A memory device includes a command interface configured to receive write commands from a host device. The memory device also includes an input buffer configured to buffer data from the host device. The memory device further includes a write shifter configured to receive a first write command of the write commands and to shift the first command through the write shifter. The write shifter is also configured to cause the input buffer to be disabled after a first threshold of clock cycles when the first write command has shifted through the write shifter. The write shifter is additionally configured to receive a second write command and prevent the input buffer from being re-enabled until the second write command has shifted through a second threshold of stages of the write shifter.

公开(公告)号：US20240005980A1

公开(公告)日：2024-01-04

申请号：US17853517

申请日：2022-06-29

Applicant: Micron Technology, Inc.

Inventor： William Chad Waldrop ,  David R. Brown ,  Guy S. Perry, IV

IPC: G11C11/4093

CPC classification number: G11C11/4093

Abstract: A memory device includes a command interface configured to receive write commands from a host device. The memory device also includes an input buffer configured to buffer data from the host device. The memory device further includes a write shifter configured to receive a first write command of the write commands and to shift the first command through the write shifter. The write shifter is also configured to cause the input buffer to be disabled after a first threshold of clock cycles when the first write command has shifted through the write shifter. The write shifter is additionally configured to receive a second write command and prevent the input buffer from being re-enabled until the second write command has shifted through a second threshold of stages of the write shifter.

公开(公告)号：US11417374B1

公开(公告)日：2022-08-16

申请号：US17178475

申请日：2021-02-18

Applicant: Micron Technology, Inc.

Inventor： William Chad Waldrop ,  Gary L. Howe

IPC: G11C7/10 ,  G11C11/4093 ,  G11C11/4076

Abstract: Systems and methods described herein provide decision feedback equalizer (DFE) circuitry that includes one or more phases. The one or more phases receive bit feedback at respective inputs of the phases. The DFE circuitry also may include variable reset circuitry. The variable reset circuitry may reset voltages of the bit feedback at inputs of each of the phases. The variable reset circuitry is configured to change its reset frequency between resets.