公开(公告)号：US20150378826A1

公开(公告)日：2015-12-31

申请号：US14848045

申请日：2015-09-08

Applicant: MICRON TECHNOLOGY, INC.

Inventor： YU ZHANG ,  Wei Bing Shang ,  En Peng Gao

IPC: G06F11/10 ,  G06F3/06

CPC classification number: G06F11/1076 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0673 ,  G06F11/1048 ,  G11C29/42 ,  G11C2029/0411 ,  H03M13/2942 ,  H03M13/6561

Abstract: One example apparatus includes a first circuit configured to receive first and second data words, to correct one or more errors in the first data word, to merge the corrected first data word and the second data word responsive to a control signal to generate a final merged data word, and to provide the final merged data word to a write circuit. The apparatus also includes a second circuit configured to also receive the first and second data words, to preliminarliy merge the first and second data words responsive to the control signal to generate an initial merged data word, to generate an initial parity code for the initial merged data word, to correct the initial parity code, and to provide the corrected parity code to the write circuit.

Abstract translation: 一个示例性设备包括：第一电路，被配置为接收第一和第二数据字，以校正第一数据字中的一个或多个错误，以响应于控制信号合并校正的第一数据字和第二数据字，以产生最终合并 数据字，并将最终合并的数据字提供给写入电路。 该装置还包括配置为还接收第一和第二数据字的第二电路，以响应于控制信号预先合并第一和第二数据字以产生初始合并数据字，以产生用于初始合并的初始奇偶校验码 数据字，以校正初始奇偶校验码，并将校正的奇偶校验码提供给写电路。