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公开(公告)号：US20210210135A1
公开(公告)日：2021-07-08
申请号：US17057428
申请日：2019-10-11
发明人： Yoshiharu MORI , Masaki KUSANO , Daisuke MATSUURA , Daisuke KOBAYASHI , Kazuyuki HIROSE , Osamu KAWASAKI
IPC分类号： G11C11/417 , G11C29/50
摘要： The purpose of the invention is to compensate for the radiation tolerance of a semiconductor memory. An apparatus (10) for compensating for radiation tolerance comprises: a voltage value acquisition unit (11) that acquires a data retention voltage value that is a maximum voltage value at which data is inverted when a power supply voltage of a semiconductor memory having a latch circuit is lowered; a correction value determination unit (12) that determines a voltage correction value on the basis of a difference between the data retention voltage value and a reference voltage value; and a voltage adjustment unit (13) that adjusts at least one among the power supply voltage and a substrate bias voltage by using the voltage correction value. The reference voltage value is set to be equal to or lower than the data retention voltage value that satisfies a required radiation tolerance.
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公开(公告)号：US20210099180A1
公开(公告)日：2021-04-01
申请号：US16970750
申请日：2019-06-05
发明人： Takanori NARITA , Daisuke MATSUURA , Shigeru ISHII , Daisuke KOBAYASHI , Kazuyuki HIROSE , Osamu KAWASAKI
IPC分类号： H03L7/093 , H03K5/1252 , H03H11/26 , H03K5/131
摘要： A semiconductor device includes first to N-th PLL circuits configured to operate in synchronization with a common reference clock signal to output first to N-th clock signals, respectively; a majority circuit that performs a majority operation on the first to N-th clock signals to generate a majority clock signal; and a filter circuit to which the majority clock signal is provided, the filter circuit operating as a low-pass filter to output an output clock signal. N is an odd number of three or more.
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公开(公告)号：US20200007124A1
公开(公告)日：2020-01-02
申请号：US16490233
申请日：2018-02-07
发明人： Daisuke MATSUURA , Takanori NARITA , Masahiro KATO , Daisuke KOBAYASHI , Kazuyuki HIROSE , Osamu KAWASAKI , Yuya KAKEHASHI , Taichi ITO
IPC分类号： H03K17/687 , H01L27/092 , H01L21/8238
摘要： An operation adjustment method of an SOI device comprises steps of: (a) obtaining a drain current-substrate bias voltage characteristic of an NMOS transistor for a source-gate voltage of 0V; (b) obtaining a lowest substrate bias voltage which turns on the NMOS transistor from the drain current-substrate bias voltage characteristic; (c) determining an upper limit of a substrate bias voltage of a PMOS transistor as a voltage obtained by subtracting a built-in potential of a pn junction from the lowest substrate bias voltage; and (d) determining the substrate bias voltage of the PMOS transistor as a positive voltage lower than the upper limit. Reduction in the power consumption and maintenance of the radiation tolerance are both achieved for the SOI device.
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