公开(公告)号：US09076964B2

公开(公告)日：2015-07-07

申请号：US14080671

申请日：2013-11-14

Applicant: Macronix International Co., Ltd.

Inventor： ChiaHua Ho ,  Erh-Kun Lai ,  Kuang-Yeu Hsieh

IPC: H01L29/00 ,  H01L45/00

CPC classification number: H01L45/1608 ,  H01L45/04 ,  H01L45/06 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/146 ,  H01L45/1625

Abstract: A bistable resistance random access memory is described for enhancing the data retention in a resistance random access memory member. A dielectric member, e.g. the bottom dielectric member, underlies the resistance random access memory member which improves the SET/RESET window in the retention of information. The deposition of the bottom dielectric member is carried out by a plasma-enhanced chemical vapor deposition or by high-density-plasma chemical vapor deposition. One suitable material for constructing the bottom dielectric member is a silicon oxide. The bistable resistance random access memory includes a bottom dielectric member disposed between a resistance random access member and a bottom electrode or bottom contact plug. Additional layers including a bit line, a top contact plug, and a top electrode disposed over the top surface of the resistance random access memory member. Sides of the top electrode and the resistance random access memory member are substantially aligned with each other.

Abstract translation: 描述了双稳态电阻随机存取存储器，用于增强电阻随机存取存储器件中的数据保持。 电介质构件，例如 底部电介质构件位于电阻随机存取存储器构件的下方，其改善了保留信息中的SET / RESET窗口。 底部电介质构件的沉积通过等离子体增强化学气相沉积或通过高密度 - 等离子体化学气相沉积来进行。 用于构造底部电介质构件的一种合适的材料是氧化硅。 双稳态随机存取存储器包括设置在电阻随机存取构件和底部电极或底部接触插塞之间的底部电介质构件。 附加层包括位线，顶部接触插塞和设置在电阻随机存取存储器构件顶表面上的顶部电极。 顶部电极和电阻随机存取存储器构件的侧面基本上彼此对准。

公开(公告)号：US08697487B2

公开(公告)日：2014-04-15

申请号：US13897109

申请日：2013-05-17

Applicant: Macronix International Co., Ltd.

Inventor： ChiaHua Ho ,  Erh-Kun Lai

IPC: H01L45/00

CPC classification number: H01L45/1683 ,  B82Y10/00 ,  G11C11/14 ,  G11C11/22 ,  G11C11/5685 ,  G11C13/0007 ,  G11C2213/32 ,  G11C2213/51 ,  G11C2213/79 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1633

Abstract: Memory devices based on tungsten-oxide memory regions are described, along with methods for manufacturing and methods for programming such devices. The tungsten-oxide memory region can be formed by oxidation of tungsten material using a non-critical mask, or even no mask at all in some embodiments. A memory device described herein includes a bottom electrode and a memory element on the bottom electrode. The memory element comprises at least one tungsten-oxygen compound and is programmable to at least two resistance states. A top electrode comprising a barrier material is on the memory element, the barrier material preventing movement of metal-ions from the top electrode into the memory element.

Abstract translation: 描述了基于氧化钨存储区域的存储器件以及用于制造的方法以及用于编程这种器件的方法。 在一些实施例中，氧化钨存储区可以通过使用非关键掩模氧化钨材料或甚至根本不进行掩模来形成。 本文描述的存储器件包括底部电极和底部电极上的存储元件。 存储元件包括至少一种钨 - 氧化合物，并且可编程为至少两个电阻状态。 包含阻挡材料的顶部电极在存储元件上，阻挡材料防止金属离子从顶部电极移动到存储元件中。

公开(公告)号：US20130260528A1

公开(公告)日：2013-10-03

申请号：US13897109

申请日：2013-05-17

Applicant: Macronix International Co., Ltd.

Inventor： ChiaHua Ho ,  Erh-Kun Lai

IPC: H01L45/00

CPC classification number: H01L45/1683 ,  B82Y10/00 ,  G11C11/14 ,  G11C11/22 ,  G11C11/5685 ,  G11C13/0007 ,  G11C2213/32 ,  G11C2213/51 ,  G11C2213/79 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1633

Abstract: Memory devices based on tungsten-oxide memory regions are described, along with methods for manufacturing and methods for programming such devices. The tungsten-oxide memory region can be formed by oxidation of tungsten material using a non-critical mask, or even no mask at all in some embodiments. A memory device described herein includes a bottom electrode and a memory element on the bottom electrode. The memory element comprises at least one tungsten-oxygen compound and is programmable to at least two resistance states. A top electrode comprising a barrier material is on the memory element, the barrier material preventing movement of metal-ions from the top electrode into the memory element.

Abstract translation: 描述了基于氧化钨存储区域的存储器件以及用于制造的方法以及用于编程这种器件的方法。 在一些实施例中，氧化钨存储区可以通过使用非关键掩模氧化钨材料或甚至根本不进行掩模来形成。 本文描述的存储器件包括底部电极和底部电极上的存储元件。 存储元件包括至少一种钨 - 氧化合物，并且可编程为至少两个电阻状态。 包含阻挡材料的顶部电极在存储元件上，阻挡材料防止金属离子从顶部电极移动到存储元件中。

公开(公告)号：US20140073108A1

公开(公告)日：2014-03-13

申请号：US14080671

申请日：2013-11-14

Applicant: Macronix International Co., Ltd.

Inventor： ChiaHua Ho ,  Erh-Kun Lai ,  Kuang-Yeu Hsieh

IPC: H01L45/00

CPC classification number: H01L45/1608 ,  H01L45/04 ,  H01L45/06 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/146 ,  H01L45/1625

Abstract: A bistable resistance random access memory is described for enhancing the data retention in a resistance random access memory member. A dielectric member, e.g. the bottom dielectric member, underlies the resistance random access memory member which improves the SET/RESET window in the retention of information. The deposition of the bottom dielectric member is carried out by a plasma-enhanced chemical vapor deposition or by high-density-plasma chemical vapor deposition. One suitable material for constructing the bottom dielectric member is a silicon oxide. The bistable resistance random access memory includes a bottom dielectric member disposed between a resistance random access member and a bottom electrode or bottom contact plug. Additional layers including a bit line, a top contact plug, and a top electrode disposed over the top surface of the resistance random access memory member. Sides of the top electrode and the resistance random access memory member are substantially aligned with each other.

Abstract translation: 描述了双稳态电阻随机存取存储器，用于增强电阻随机存取存储器件中的数据保持。 电介质构件，例如 底部电介质构件位于电阻随机存取存储器构件的下方，其改善了保留信息中的SET / RESET窗口。 底部电介质构件的沉积通过等离子体增强化学气相沉积或通过高密度 - 等离子体化学气相沉积来进行。 用于构造底部电介质构件的一种合适的材料是氧化硅。 双稳态随机存取存储器包括设置在电阻随机存取构件和底部电极或底部接触插塞之间的底部电介质构件。 附加层包括位线，顶部接触插塞和设置在电阻随机存取存储器构件顶表面上的顶部电极。 顶部电极和电阻随机存取存储器构件的侧面基本上彼此对准。