公开(公告)号：US4503598A

公开(公告)日：1985-03-12

申请号：US380170

申请日：1982-05-20

申请人： Madhukar B. Vora ,  Vikram M. Patel

发明人： Madhukar B. Vora ,  Vikram M. Patel

IPC分类号： H01L21/336 ,  H01L23/485 ,  H01L29/10 ,  H01L29/78 ,  H01L21/22 ,  H01L21/467

CPC分类号： H01L29/7802 ,  H01L23/485 ,  H01L29/1095 ,  H01L29/41766 ,  H01L2924/0002

摘要： A power MOSFET semiconductor structure is fabricated using the steps of depositing an epitaxial layer 12 of N conductivity type silicon on an underlying silicon substrate 10 of N conductivity type, forming a plurality of polycrystalline silicon electrodes 18 on the epitaxial layer 12, each electrode 18 being separated from the epitaxial layer 12 by a layer of insulating material 15; introducing P 30 and N 33 conductivity type impurities into the epitaxial layer 12 between the electrodes 18, the P type impurity 30 underlying the N type impurity 33; removing regions of the epitaxial layer 12 to form openings 21 in the epitaxial layer 12 between the electrodes 18, the removed regions 21 extending through the N type region 33 but not through the P type region 30; and depositing electrically conductive material 40 in the opening 23.The resulting semiconductor structure includes an N type substrate 10, an N type epitaxial layer 12, an opening 21 in the epitaxial layer 12 extending downward a selected distance, an upper N type region 33 surrounding the opening 21 and extending to the surface of the epitaxial layer 12, a lower P type region 30 which extends to the surface of the epitaxial layer 12 and everywhere separates the N type region 33 from epitaxial layer 12, an electrode 40 formed in the opening and extending to the upper surface of the epitaxial layer 12, and a second electrode 18 disposed above epitaxial layer 12 and separated from it by insulating material 15.

摘要翻译： 使用以下步骤制造功率MOSFET半导体结构：在N导电类型的下面的硅衬底10上沉积N导电型硅的外延层12，在外延层12上形成多个多晶硅电极18，每个电极18为 通过绝缘材料层15与外延层12分离; 将P 30和N 33导电型杂质引入电极18之间的外延层12，N型杂质33下面的P型杂质30; 去除外延层12的区域，以在电极18之间的外延层12中形成开口21，延伸穿过N型区域33而不通过P型区域30的去除区21; 并且将导电材料40沉积在开口23中。所得的半导体结构包括N型衬底10，N型外延层12，外延层12中向下延伸选定距离的开口21，周围的上N型区域33 开口21并且延伸到外延层12的表面;延伸到外延层12的表面的下部P型区域30，其中N型区域33与外延层12分开，形成在开口中的电极40 并延伸到外延层12的上表面，以及设置在外延层12上方并由绝缘材料15分离的第二电极18。