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    System and method for routing connections with improved interconnect thickness
    3.
    发明授权
    System and method for routing connections with improved interconnect thickness 有权
    用于路由连接的系统和方法具有改进的互连厚度

    公开(公告)号：US08042076B2

    公开(公告)日：2011-10-18

    申请号：US12115991

    申请日：2008-05-06

    申请人： Payman Zarkesh-Ha ,  Christopher L. Hamlin ,  Ashok K. Kapoor ,  James S. Koford ,  Madhukar B. Vora

    发明人： Payman Zarkesh-Ha ,  Christopher L. Hamlin ,  Ashok K. Kapoor ,  James S. Koford ,  Madhukar B. Vora

    IPC分类号： G06F17/50

    CPC分类号： H01L23/5283 ,  G06F17/5077 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for modeling a circuit includes generating a circuit model based on a netlist that defines a plurality of connections between a plurality of circuit elements. The circuit model includes a model of one or more of the circuit elements. The method further includes determining a wire width associated with at least a selected connection based, at least in part, on design rules associated with the netlist. Additionally, the method includes determining a wire thickness associated with the selected connection based, at least in part, on a signal delay associated with the wire thickness. Furthermore, the method also includes routing the selected connection in the circuit model using a wire having a width substantially equal to the wire width calculated for the connection and a thickness equal to the wire thickness calculated for the connection and storing the circuit model in an electronic storage media.

    摘要翻译： 一种用于对电路进行建模的方法包括基于限定多个电路元件之间的多个连接的网表生成电路模型。 电路模型包括一个或多个电路元件的模型。 该方法还包括至少部分地基于与网表相关联的设计规则来确定与至少所选连接相关联的线宽度。 另外，该方法包括至少部分地基于与线材厚度相关联的信号延迟来确定与所选择的连接相关联的线材厚度。 此外，该方法还包括使用具有基本上等于为连接计算出的线宽度的宽度的线和对于连接计算的线厚度等于电路模型中的所选择的连接来路由所选择的连接，并将电路模型存储在电子 储存媒介。

    Method of forming an oxide isolated metal silicon-gate JFET
    4.
    发明授权
    Method of forming an oxide isolated metal silicon-gate JFET 失效
    形成氧化物隔离金属硅栅极JFET的方法

    公开(公告)号：US07713804B2

    公开(公告)日：2010-05-11

    申请号：US12276574

    申请日：2008-11-24

    申请人： Madhukar B. Vora ,  Ashok K. Kapoor

    发明人： Madhukar B. Vora ,  Ashok K. Kapoor

    IPC分类号： H01L21/337

    CPC分类号： H01L29/808 ,  H01L29/66901

    摘要： A JFET structure with self-aligned metal source, drain and gate contacts with very low resistivity and very small feature sizes. Small source, drain and gate openings are etched in a thin dielectric layer which has a thickness set according to the desired source, gate and drain opening sizes, said dielectric layer having a nitride top layer. Metal is deposited on top of said dielectric layer to fill said openings and the metal is polished back to the top of the dielectric layer to achieve thin source, drain and gate contacts. Some embodiments include an anti-leakage poly-silicon layer lining the contact holes and all embodiments where spiking may occur include a barrier metal layer.

    摘要翻译： 具有自对准金属源，漏极和栅极接触的JFET结构，具有非常低的电阻率和非常小的特征尺寸。 小的源极，漏极和栅极开口被蚀刻在具有根据期望的源极，栅极和漏极开口尺寸设置的厚度的薄介电层中，所述介电层具有氮化物顶层。 金属沉积在所述电介质层的顶部以填充所述开口并且金属被抛光回到电介质层的顶部以实现薄的源极，漏极和栅极接触。 一些实施例包括衬在接触孔上的防漏多晶硅层，并且可能发生尖峰的所有实施例包括阻挡金属层。

    Programmable switch circuit and method, method of manufacture, and devices and systems including the same
    5.
    发明授权
    Programmable switch circuit and method, method of manufacture, and devices and systems including the same 失效
    可编程开关电路及方法，制造方法以及包括其的装置和系统

    公开(公告)号：US07710148B2

    公开(公告)日：2010-05-04

    申请号：US12156565

    申请日：2008-06-02

    申请人： Madhukar B. Vora

    发明人： Madhukar B. Vora

    IPC分类号： H01L25/00 ,  H03K19/177

    CPC分类号： H03K19/173 ,  H01L2924/0002 ,  H03K19/17736 ,  H03K19/1778 ,  H01L2924/00

    摘要： A switching circuit can include a logic circuit having a logic circuit input and a logic circuit output and at least three input transistors coupled to provide three separate paths between three input/output (I/O) nodes and the logic circuit input. The switching circuit can further include at least three output transistors coupled to provide three separate paths between the three I/O nodes and the logic circuit output. Methods of fabricating such switch circuits and devices and/or systems including such switching circuits are also disclosed.

    摘要翻译： 开关电路可以包括具有逻辑电路输入和逻辑电路输出的逻辑电路以及耦合以在三个输入/输出（I / O）节点和逻辑电路输入之间提供三个独立路径的至少三个输入晶体管。 开关电路还可以包括耦合到三个I / O节点和逻辑电路输出之间的三个独立路径的至少三个输出晶体管。 还公开了制造这种开关电路和包括这种开关电路的装置和/或系统的方法。

    Scalable process and structure of JFET for small and decreasing line widths
    6.
    发明授权
    Scalable process and structure of JFET for small and decreasing line widths 失效
    适用于JFET的可扩展的工艺和结构，可减小和减少线宽

    公开(公告)号：US07642566B2

    公开(公告)日：2010-01-05

    申请号：US11451886

    申请日：2006-06-12

    申请人： Madhukar B. Vora ,  Ashok Kumar Kapoor

    发明人： Madhukar B. Vora ,  Ashok Kumar Kapoor

    IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC分类号： H04L7/0337 ,  H01L21/2257 ,  H01L21/76816 ,  H01L21/76897 ,  H01L29/66901 ,  H01L29/808 ,  H01L2924/0002 ,  H03L7/0812 ,  H04L7/0037 ,  H01L2924/00

    摘要： A scalable device structure and process for forming a normally off JFET with 45 NM linewidths or less. The contacts to the source, drain and gate areas are formed by forming a layer of oxide of a thickness of less than 1000 angstroms, and, preferably 500 angstroms or less on top of the substrate. A nitride layer is formed on top of the oxide layer and holes are etched for the source, drain and gate contacts. A layer of polysilicon is then deposited so as to fill the holes and the polysilicon is polished back to planarize it flush with the nitride layer. The polysilicon contacts are then implanted with the types of impurities necessary for the channel type of the desired transistor and the impurities are driven into the semiconductor substrate below to form source, drain and gate regions.

    摘要翻译： 用于形成45 N线宽以下的常闭JFET的可扩展器件结构和工艺。 源极，漏极和栅极区域的触点通过在衬底的顶部上形成厚度小于1000埃，优选为500埃或更小的氧化物层而形成。 在氧化物层的顶部形成氮化物层，蚀刻用于源极，漏极和栅极接触的孔。 然后沉积多晶硅层以填充孔，并且将多晶硅抛光回去以使其与氮化物层齐平。 然后将多晶硅触点注入所需晶体管的沟道类型所需的杂质类型，并将杂质驱动到下面的半导体衬底中以形成源极，漏极和栅极区域。

    Junction isolated poly-silicon gate JFET
    7.
    发明申请
    Junction isolated poly-silicon gate JFET 审中-公开
    结隔离多晶硅栅JFET

    公开(公告)号：US20080128762A1

    公开(公告)日：2008-06-05

    申请号：US11590376

    申请日：2006-10-31

    申请人： Madhukar B. Vora

    发明人： Madhukar B. Vora

    IPC分类号： H01L29/76 ,  H01L21/337

    CPC分类号： H01L29/808 ,  H01L27/098 ,  H01L29/66901

    摘要： An integrated Junction Field Effect Transistor is disclosed which is much smaller and much less expensive to fabricate because it does not use Shallow Trench Isolation or field oxide in the semiconductor substrate to isolate separate transistors. Instead, a layer of insulating material is formed on the top surface of said substrate, and interconnect trenches are etched in said insulating layer which do not go all the way down to the semiconductor substrate. Contact openings are etched in the insulating layer all the way down to the semiconductor layer. Doped poly-silicon is formed in the contact openings and interconnect trenches and silicide is formed on tops of the poly-silicon. This contact and interconnect structure applies to any integrated transistor. The integrated JFET disclosed herein does not use STI or field oxide and uses junction isolation. A conventional JFET is built in a P-well. The P-well is encapsulated in an N-well which is implanted into the substrate. Separate contacts to the P-well, N-well and substrate are formed as well as to the source, drain and gate so that the device can be isolated by reverse-biasing a PN junction. Operating voltage is restricted to less than 0.7 volts to prevent latching.

    摘要翻译： 公开了一种集成结型场效应晶体管，其制造要小得多，成本更低，因为它不在半导体衬底中使用浅沟槽隔离或场氧化物来隔离单独的晶体管。 相反，在所述衬底的顶表面上形成绝缘材料层，并且在所述绝缘层中蚀刻互连沟槽，所述绝缘层不会完全向下到达半导体衬底。 接触开口在绝缘层中一直被蚀刻到半导体层。 掺杂的多晶硅形成在接触开口和互连沟槽中，硅化物形成在多晶硅的顶部。 该接触和互连结构适用于任何集成的晶体管。 本文公开的集成JFET不使用STI或场氧化物并且使用结隔离。 传统的JFET内置在P阱中。 P阱被封装在植入衬底中的N阱中。 形成与P阱，N阱和衬底的单独接触以及源极，漏极和栅极，使得可以通过反向偏置PN结来隔离器件。 工作电压限制在小于0.7伏，以防止锁定。

    Process for fabricating complementary contactless vertical bipolar transistors
    8.
    发明授权
    Process for fabricating complementary contactless vertical bipolar transistors 失效
    互补非接触垂直双极晶体管的制造工艺

    公开(公告)号：US5055418A

    公开(公告)日：1991-10-08

    申请号：US614182

    申请日：1990-11-13

    申请人： Madhukar B. Vora

    发明人： Madhukar B. Vora

    IPC分类号： H01L21/8228 ,  H01L27/082

    CPC分类号： H01L21/82285 ,  H01L27/0826 ,  Y10S148/01 ,  Y10S148/011

    摘要： A complementary NPN and PNP contactless vertical transistor structure is formed by a process that includes the steps of providing: (1) a buried layer and P-- tub for NPN; (2) a channel stopper for NPN, and a buried layer for PNP; (3) isolation oxide for NPN and PNP; (4) a sink for NPN, and a ground for PNP; (5) a base for NPN, and a sink for PNP; (6) a base for PNP; (7) a N+ poly implant for NPN emitter and PNP extrinsic base; (8) a P+ poly implant for NPN extrinsic base and PNP emitter; (9) poly definition; (10) silicide exclusion for resistors and diodes; (11) contacts; (12) first metal; (13) vias; (14) second metal; and (15) scratch protection.

    摘要翻译： 通过包括以下步骤的方法形成互补的NPN和PNP非接触垂直晶体管结构：（1）用于NPN的掩埋层和P-桶; （2）用于NPN的通道止动器和用于PNP的掩埋层; （3）NPN和PNP的隔离氧化物; （4）NPN的水槽和PNP的地面; （5）NPN基地和PNP汇; （6）PNP基地; （7）NPN发射极和PNP外在基极的N +多晶种植体; （8）用于NPN外在碱和PNP发射体的P +多晶种植体; （9）多分辨率; （10）电阻和二极管的硅化物排除; （11）接触; （12）第一金属; （13）通道; （14）第二金属; 和（15）划伤保护。

    Bipolar transistor with polysilicon stringer base contact
    9.
    发明授权
    Bipolar transistor with polysilicon stringer base contact 失效
    双极晶体管与多晶硅基板接触

    公开(公告)号：US4974046A

    公开(公告)日：1990-11-27

    申请号：US248300

    申请日：1988-09-21

    申请人： Madhukar B. Vora

    发明人： Madhukar B. Vora

    IPC分类号： H01L21/331 ,  H01L21/60 ,  H01L29/417 ,  H01L29/423

    CPC分类号： H01L21/76897 ,  H01L29/41708 ,  H01L29/42304 ,  H01L29/66272 ,  Y10S257/90

    摘要： There is disclosed herein a base and emitter contact structure for a bipolar transistor which is comprised of a polysilicon stripe over an isolation island which stripe extends to a position external to the position of the isolation island and assumes the shape of an emitter contact pad. The emitter contact stripe has a layer of self aligned silicide formed thereover to lower its resistance, and this silicide is doped with both N and P type impurities one of which is selected to have a higher rate of diffusion than the other. A layer of self aligned insulating material is formed over the silicide and polysilicon of the emitter contact stripe. There are anisotropically etched insulating spacers formed on the sides of the emitter contact stripe, and there are silicide base contact stringers formed beside the spacers by anisotropic etching of a layer of doped silicide. A heat drive in step in the process used to make the structure, also disclosed herein, causes the impurities from the two silicide layers to diffuse into the emitter contact polysilicon and into the epitaxially grown silicon in the isolation island. An emitter and a base are and the the attendant base-emitter and base-collector junctions are formed because the faster diffusing impurity overtakes the slower diffusion impurity and passes it to thereby form the base region. The impurities from the base contact stringers also diffuse into the epitaxially grown silicon and their lateral diffusion causes them to link up with the base impurities which have diffused into the epitaxially grown silicon from the silicide over the emitter contact polysilicon.

    摘要翻译： 这里公开了一种用于双极晶体管的基极和发射极接触结构，其包括隔离岛上的多晶硅条纹，该条纹延伸到隔离岛的位置外的位置，并呈现发射极接触焊盘的形状。 发射极接触条纹具有形成在其上的自对准硅化物层以降低其电阻，并且该硅化物掺杂有N型和P型杂质，其中一种杂质被选择为具有比另一种更高的扩散速率。 在发射极接触条纹的硅化物和多晶硅之上形成自对准绝缘材料层。 存在形成在发射极接触条的侧面上的各向异性蚀刻的绝缘间隔物，并且通过各向异性蚀刻掺杂的硅化物层，在间隔物旁边形成有硅化物基极接触桁条。 在本文也公开的用于制造结构的工艺中的步骤中的热驱动导致来自两个硅化物层的杂质扩散到发射极接触多晶硅中并进入隔离岛中的外延生长的硅中。 发射极和基极是形成的，因为较快的扩散杂质超过较慢的扩散杂质并通过它从而形成基极区，因此形成了伴随的基极 - 基极 - 集电极结。 来自基底接触桁条的杂质也扩散到外延生长的硅中，并且它们的横向扩散使它们与发射极接触多晶硅上的硅化物扩散到外延生长的硅中的基本杂质连接。