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    Method of fabricating power MOSFET structure utilizing self-aligned diffusion and etching techniques
    1.
    发明授权
    Method of fabricating power MOSFET structure utilizing self-aligned diffusion and etching techniques 失效
    使用自对准扩散和蚀刻技术制造功率MOSFET结构的方法

    公开(公告)号：US4503598A

    公开(公告)日：1985-03-12

    申请号：US380170

    申请日：1982-05-20

    申请人： Madhukar B. Vora ,  Vikram M. Patel

    发明人： Madhukar B. Vora ,  Vikram M. Patel

    IPC分类号： H01L21/336 ,  H01L23/485 ,  H01L29/10 ,  H01L29/78 ,  H01L21/22 ,  H01L21/467

    CPC分类号： H01L29/7802 ,  H01L23/485 ,  H01L29/1095 ,  H01L29/41766 ,  H01L2924/0002

    摘要： A power MOSFET semiconductor structure is fabricated using the steps of depositing an epitaxial layer 12 of N conductivity type silicon on an underlying silicon substrate 10 of N conductivity type, forming a plurality of polycrystalline silicon electrodes 18 on the epitaxial layer 12, each electrode 18 being separated from the epitaxial layer 12 by a layer of insulating material 15; introducing P 30 and N 33 conductivity type impurities into the epitaxial layer 12 between the electrodes 18, the P type impurity 30 underlying the N type impurity 33; removing regions of the epitaxial layer 12 to form openings 21 in the epitaxial layer 12 between the electrodes 18, the removed regions 21 extending through the N type region 33 but not through the P type region 30; and depositing electrically conductive material 40 in the opening 23.The resulting semiconductor structure includes an N type substrate 10, an N type epitaxial layer 12, an opening 21 in the epitaxial layer 12 extending downward a selected distance, an upper N type region 33 surrounding the opening 21 and extending to the surface of the epitaxial layer 12, a lower P type region 30 which extends to the surface of the epitaxial layer 12 and everywhere separates the N type region 33 from epitaxial layer 12, an electrode 40 formed in the opening and extending to the upper surface of the epitaxial layer 12, and a second electrode 18 disposed above epitaxial layer 12 and separated from it by insulating material 15.

    摘要翻译： 使用以下步骤制造功率MOSFET半导体结构：在N导电类型的下面的硅衬底10上沉积N导电型硅的外延层12，在外延层12上形成多个多晶硅电极18，每个电极18为 通过绝缘材料层15与外延层12分离; 将P 30和N 33导电型杂质引入电极18之间的外延层12，N型杂质33下面的P型杂质30; 去除外延层12的区域，以在电极18之间的外延层12中形成开口21，延伸穿过N型区域33而不通过P型区域30的去除区21; 并且将导电材料40沉积在开口23中。所得的半导体结构包括N型衬底10，N型外延层12，外延层12中向下延伸选定距离的开口21，周围的上N型区域33 开口21并且延伸到外延层12的表面;延伸到外延层12的表面的下部P型区域30，其中N型区域33与外延层12分开，形成在开口中的电极40 并延伸到外延层12的上表面，以及设置在外延层12上方并由绝缘材料15分离的第二电极18。

    JFET with built in back gate in either SOI or bulk silicon
    2.
    发明授权
    JFET with built in back gate in either SOI or bulk silicon 失效
    JFET内置在SOI或体硅中的背栅

    公开(公告)号：US07557393B2

    公开(公告)日：2009-07-07

    申请号：US11502172

    申请日：2006-08-10

    申请人： Madhukar B. Vora

    发明人： Madhukar B. Vora

    IPC分类号： H01L31/112

    CPC分类号： H01L29/42316 ,  H01L29/1066 ,  H01L29/66901 ,  H01L29/808

    摘要： A Junction Field-Effect transistor with no surface contact for the back gate and twice as much transconductance in the channel and with a higher switching speed is achieved by intentionally shorting the channel-well PN junction with the gate region. This is achieved by intentionally etching away field oxide outside the active area at least in the gate region so as to expose the sidewalls of the active area down to the channel-well PN junction or a buried gate which is in electrical contact with the well. Polysilicon is then deposited in the trench and doped heavily and an anneal step is used to drive impurities into the top and sidewalls of the channel region thereby creating a “wrap-around” gate region which reaches down the sidewalls of the channel region to the channel-well PN junction. This causes the bias applied to the gate terminal to also be applied to the well thereby modulating the channel transconductance with the depletion regions around both the gate-channel PN junction and the channel-well PN junction.

    摘要翻译： 通过有意短路与栅极区域的沟道阱PN结，实现了对栅极没有表面接触并且在沟道中具有两倍跨导的结场场效应晶体管，并具有较高的开关速度。 这是通过有意地至少在栅极区域中去除有源区域外的场氧化物来实现的，以便将有源区域的侧壁向下暴露于沟道阱PN结或与阱电接触的掩埋栅极。 然后将多晶硅沉积在沟槽中并进行大量掺杂，并且使用退火步骤将杂质驱动到沟道区的顶部和侧壁中，从而形成“环绕”栅极区，其向下延伸到沟道区的侧壁 - PN结。 这导致施加到栅极端子的偏置也被施加到阱，从而调制与栅极 - 沟道PN结和通道阱PN结两端的耗尽区的沟道跨导。

    Oxide Isolated Metal Silicon-Gate JFET
    3.
    发明申请
    Oxide Isolated Metal Silicon-Gate JFET 失效
    氧化物隔离金属硅栅极JFET

    公开(公告)号：US20090142889A1

    公开(公告)日：2009-06-04

    申请号：US12276574

    申请日：2008-11-24

    申请人： Madhukar B. Vora ,  Ashok Kumar Kapoor

    发明人： Madhukar B. Vora ,  Ashok Kumar Kapoor

    IPC分类号： H01L21/337

    CPC分类号： H01L29/808 ,  H01L29/66901

    摘要： A JFET structure with self-aligned metal source, drain and gate contacts with very low resistivity and very small feature sizes. Small source, drain and gate openings are etched in a thin dielectric layer which has a thickness set according to the desired source, gate and drain opening sizes, said dielectric layer having a nitride top layer. Metal is deposited on top of said dielectric layer to fill said openings and the metal is polished back to the top of the dielectric layer to achieve thin source, drain and gate contacts. Some embodiments include an anti-leakage poly-silicon layer lining the contact holes and all embodiments where spiking may occur include a barrier metal layer.

    摘要翻译： 具有自对准金属源，漏极和栅极接触的JFET结构，具有非常低的电阻率和非常小的特征尺寸。 小的源极，漏极和栅极开口被蚀刻在具有根据期望的源极，栅极和漏极开口尺寸设置的厚度的薄介电层中，所述介电层具有氮化物顶层。 金属沉积在所述电介质层的顶部以填充所述开口并且金属被抛光回到电介质层的顶部以实现薄的源极，漏极和栅极接触。 一些实施例包括衬在接触孔上的防漏多晶硅层，并且可能发生尖峰的所有实施例包括阻挡金属层。

    Semiconductor device, design method and structure
    4.
    发明申请
    Semiconductor device, design method and structure 有权
    半导体器件，设计方法和结构

    公开(公告)号：US20080099873A1

    公开(公告)日：2008-05-01

    申请号：US11590265

    申请日：2006-10-31

    申请人： Madhukar B. Vora

    发明人： Madhukar B. Vora

    IPC分类号： H01L29/00

    CPC分类号： H01L27/11 ,  Y10S257/903

    摘要： A semiconductor device can include at least a first diffusion region formed by doping a semiconductor substrate and at least a second diffusion region formed by doping the semiconductor substrate that is separated from the first diffusion region by an isolation region. At least a first conductive line can comprise a semiconductor material formed over and in contact with the first diffusion region and the second diffusion region. A portion of the first conductive line in contact with the first diffusion region is doped to an opposite conductivity type as the first diffusion region. At least a second conductive line comprising a semiconductor material is formed in parallel with the first conductive line and over and in contact with the first diffusion region and the second diffusion region. A portion of the second conductive line can be in contact with the first diffusion region and doped to a same conductivity type as the first diffusion region. A portion of the second conductive line in contact with the second diffusion region can be doped to a same conductivity type as the second diffusion region.

    摘要翻译： 半导体器件可以包括通过掺杂半导体衬底形成的至少第一扩散区域和至少通过掺杂通过隔离区域与第一扩散区域分离的半导体衬底形成的第二扩散区域。 至少第一导电线可以包括形成在第一扩散区域和第二扩散区域上并与其接触的半导体材料。 与第一扩散区接触的第一导电线的一部分被掺杂成与第一扩散区相反的导电类型。 包括半导体材料的至少第二导电线与第一导电线平行地形成并且与第一扩散区和第二扩散区相接触并接触。 第二导线的一部分可以与第一扩散区接触并掺杂成与第一扩散区相同的导电类型。 可以将与第二扩散区接触的第二导线的一部分掺杂成与第二扩散区相同的导电类型。

    Oxide isolated metal silicon-gate JFET
    5.
    发明申请
    Oxide isolated metal silicon-gate JFET 失效
    氧化物隔离金属硅栅JFET

    公开(公告)号：US20080014687A1

    公开(公告)日：2008-01-17

    申请号：US11484402

    申请日：2006-07-11

    申请人： Madhukar B. Vora ,  Ashok Kumar Kapoor

    发明人： Madhukar B. Vora ,  Ashok Kumar Kapoor

    IPC分类号： H01L21/337

    CPC分类号： H01L29/808 ,  H01L29/66901

    摘要： A JFET structure with self-aligned metal source, drain and gate contacts with very low resistivity and very small feature sizes. Small source, drain and gate openings are etched in a thin dielectric layer which has a thickness set according to the desired source, gate and drain opening sizes, said dielectric layer having a nitride top layer. Metal is deposited on top of said dielectric layer to fill said openings and the metal is polished back to the top of the dielectric layer to achieve thin source, drain and gate contacts. Some embodiments include an anti-leakage poly-silicon layer lining the contact holes and all embodiments where spiking may occur include a barrier metal layer.

    摘要翻译： 具有自对准金属源，漏极和栅极接触的JFET结构，具有非常低的电阻率和非常小的特征尺寸。 小的源极，漏极和栅极开口被蚀刻在具有根据期望的源极，栅极和漏极开口尺寸设置的厚度的薄介电层中，所述介电层具有氮化物顶层。 金属沉积在所述电介质层的顶部以填充所述开口并且金属被抛光回到电介质层的顶部以实现薄的源极，漏极和栅极接触。 一些实施例包括衬在接触孔上的防漏多晶硅层，并且可能发生尖峰的所有实施例包括阻挡金属层。

    BiCMOS multiplexers and crossbar switches
    6.
    发明授权
    BiCMOS multiplexers and crossbar switches 失效
    BiCMOS多路复用器和交叉开关

    公开(公告)号：US5570059A

    公开(公告)日：1996-10-29

    申请号：US375303

    申请日：1995-01-20

    申请人： Madhukar B. Vora ,  Burnell G. West

    发明人： Madhukar B. Vora ,  Burnell G. West

    IPC分类号： H01L21/8249 ,  H01L27/06 ,  H03K17/00 ,  H03K17/62 ,  H03K19/086 ,  H03K19/173 ,  H03K17/60

    CPC分类号： H03K17/6285 ,  H03K17/6257 ,  H03K19/1737

    摘要： A high speed switching technology suitable for implementing field programmable gate arrays using current mode logic in the high speed data path, and CMOS steering logic outside the high speed data path to enable the high speed switching logic and to implement multiplexer, selector and crossbar switch functions. High speed emitter follower logic compatible with the high speed switching logic for level shifting, buffering, and providing more current sink or source capacity is also disclosed.

    摘要翻译： 适用于在高速数据通路中使用电流模式逻辑实现现场可编程门阵列的高速开关技术，以及高速数据通路外的CMOS转向逻辑，以实现高速开关逻辑和实现多路复用器，选择器和交叉开关功能 。 还公开了与高速开关逻辑兼容的高速射极跟随器逻辑，用于电平转换，缓冲和提供更多的电流吸收或源极容量。

    Method of making small contactless RAM cell
    7.
    发明授权
    Method of making small contactless RAM cell 失效
    制作小型非接触式RAM单元的方法

    公开(公告)号：US5100824A

    公开(公告)日：1992-03-31

    申请号：US701542

    申请日：1991-05-16

    申请人： Madhukar B. Vora

    发明人： Madhukar B. Vora

    IPC分类号： H01L21/8244 ,  H01L21/8249 ,  H01L27/11 ,  H01L29/04 ,  H01L29/08 ,  H01L29/45

    CPC分类号： H01L21/8249 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1108 ,  H01L29/04 ,  H01L29/0847 ,  H01L29/456

    摘要： There is disclosed a static RAM cell and MOS device for making the cell along with a process for making the types or devices disclosed. The devices is an MOS device built in an isolated island of epitaxial silicon similar to bipolar device isolation islands, and has single level polysilicon with self-aligned silicide coating for source, drain and gate contacts such that no contact windows need be formed inside the isolation island to make contact with the transistor. The static RAM cell formed using this device uses extensions of the polysilicon contacts outside the isolation islands as shared nodes to implement the conventional cross coupling of various gates to drain and source electrodes of the other transistors in the flip flop. Similarly, extensions of various gate, source and drain contact electrodes are used as shared word lines, and shared Vcc and ground contacts.

    摘要翻译： 公开了一种用于制造单元的静态RAM单元和MOS器件以及用于制造所公开的类型或器件的过程。 器件是一种MOS器件，内置隔离孤岛孤岛，与双极器件隔离岛类似，具有单层多晶硅，具有源极，漏极和栅极接触的自对准硅化物涂层，从而不需要在隔离层内形成接触窗口 岛与晶体管接触。 使用该器件形成的静态RAM单元使用隔离岛外部的多晶硅触点的扩展作为共享节点，以实现各种门到触发器中其他晶体管的漏极和源极的常规交叉耦合。 类似地，各种栅极，源极和漏极接触电极的扩展用作共享字线，共享Vcc和接地触点。

    Low resistance Schottky diode on polysilicon/metal-silicide
    8.
    发明授权
    Low resistance Schottky diode on polysilicon/metal-silicide 失效
    多晶硅/金属硅化物上的低电阻肖特基二极管

    公开(公告)号：US4908679A

    公开(公告)日：1990-03-13

    申请号：US570408

    申请日：1984-01-12

    申请人： Madhukar B. Vora ,  Hemraj K. Hingarh

    发明人： Madhukar B. Vora ,  Hemraj K. Hingarh

    IPC分类号： H01L21/329 ,  H01L21/70 ,  H01L21/84 ,  H01L29/04 ,  H01L29/872

    CPC分类号： H01L29/66143 ,  H01L21/70 ,  H01L21/84 ,  H01L29/04 ,  H01L29/872

    摘要： A Schottky diode is fabricated according to the following steps: forming a layer of metal-silicide on an underlying dielectric layer, forming a polysilicon layer on the upper surface of the metal-silicide layer, forming a second dielectric layer on the upper surface of the polysilicon layer and patterning the second dielectric layer to create a contact window through the second dielectric layer to an exposed surface region of the polysilicon layer, and forming a metal contact to the exposed surface region.

    摘要翻译： 根据以下步骤制造肖特基二极管：在下面的介电层上形成金属硅化物层，在金属硅化物层的上表面上形成多晶硅层，在第二电介质层的上表面上形成第二电介质层 多晶硅层和图案化第二电介质层以形成通过第二电介质层的接触窗到多晶硅层的暴露表面区域，以及形成与暴露表面区域的金属接触。