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公开(公告)号：US20140040543A1
公开(公告)日：2014-02-06
申请号：US14048451
申请日：2013-10-08
申请人： Mahesh Natu , Thanunathan Rangarajan , Gautam Doshi , Shamanna M. Datta , Baskaran Ganesan , Mohan J. Kumar , Rajesh S. Parthasarathy , Frank Binns , Rajesh Nagaraja Murthy , Robert C. Swanson
发明人： Mahesh Natu , Thanunathan Rangarajan , Gautam Doshi , Shamanna M. Datta , Baskaran Ganesan , Mohan J. Kumar , Rajesh S. Parthasarathy , Frank Binns , Rajesh Nagaraja Murthy , Robert C. Swanson
IPC分类号： G11C7/10
CPC分类号： G06F13/24 , G06F9/30101 , G06F9/3017 , G06F9/30189 , G06F9/3851 , G06F9/461 , G11C7/1072 , G11C11/40615
摘要： In one embodiment, the present invention includes a processor that has an on-die storage such as a static random access memory to store an architectural state of one or more threads that are swapped out of architectural state storage of the processor on entry to a system management mode (SMM). In this way communication of this state information to a system management memory can be avoided, reducing latency associated with entry into SMM. Embodiments may also enable the processor to update a status of executing agents that are either in a long instruction flow or in a system management interrupt (SMI) blocked state, in order to provide an indication to agents inside the SMM. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，本发明包括具有诸如静态随机存取存储器之类的片上存储器的处理器，用于存储在进入系统时从处理器的架构状态存储器交换的一个或多个线程的架构状态 管理模式（SMM）。 以这种方式，可以避免该状态信息与系统管理存储器的通信，减少与进入SMM相关联的延迟。 实施例还可以使处理器更新处于长指令流或处于系统管理中断（SMI）阻塞状态中的执行代理的状态，以向SMM内的代理提供指示。 描述和要求保护其他实施例。
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公开(公告)号：US20110055469A1
公开(公告)日：2011-03-03
申请号：US12550737
申请日：2009-08-31
申请人： Mahesh S. Natu , Thanunathan Rangarajan , Gautam B. Doshi , Shammanna M. Datta , Baskaran Ganesan , Mohan J. Kumar , Rajesh S. Parthasarathy , Frank Binns , Rajesh Nagaraja Murthy , Robert C. Swanson
发明人： Mahesh S. Natu , Thanunathan Rangarajan , Gautam B. Doshi , Shammanna M. Datta , Baskaran Ganesan , Mohan J. Kumar , Rajesh S. Parthasarathy , Frank Binns , Rajesh Nagaraja Murthy , Robert C. Swanson
IPC分类号： G06F12/06
CPC分类号： G06F13/24 , G06F9/30101 , G06F9/3017 , G06F9/30189 , G06F9/3851 , G06F9/461 , G11C7/1072 , G11C11/40615
摘要： In one embodiment, the present invention includes a processor that has an on-die storage such as a static random access memory to store an architectural state of one or more threads that are swapped out of architectural state storage of the processor on entry to a system management mode (SMM). In this way communication of this state information to a system management memory can be avoided, reducing latency associated with entry into SMM. Embodiments may also enable the processor to update a status of executing agents that are either in a long instruction flow or in a system management interrupt (SMI) blocked state, in order to provide an indication to agents inside the SMM. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，本发明包括具有诸如静态随机存取存储器之类的片上存储器的处理器，用于存储在进入系统时从处理器的架构状态存储器交换的一个或多个线程的架构状态 管理模式（SMM）。 以这种方式，可以避免该状态信息与系统管理存储器的通信，减少与进入SMM相关联的延迟。 实施例还可以使处理器更新处于长指令流或处于系统管理中断（SMI）阻塞状态中的执行代理的状态，以向SMM内的代理提供指示。 描述和要求保护其他实施例。
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3.发明授权Enabling storage of active state in internal storage of processor rather than in SMRAM upon entry to system management mode 有权在进入系统管理模式时，将活动状态存储在处理器的内部存储器中，而不是在SMRAM中公开(公告)号：US08578138B2
公开(公告)日：2013-11-05
申请号：US12550737
申请日：2009-08-31
申请人： Mahesh S. Natu , Thanunathan Rangarajan , Gautam B. Doshi , Shammanna M. Datta , Baskaran Ganesan , Mohan J. Kumar , Rajesh S. Parthasarathy , Frank Binns , Rajesh Nagaraja Murthy , Robert C. Swanson
发明人： Mahesh S. Natu , Thanunathan Rangarajan , Gautam B. Doshi , Shammanna M. Datta , Baskaran Ganesan , Mohan J. Kumar , Rajesh S. Parthasarathy , Frank Binns , Rajesh Nagaraja Murthy , Robert C. Swanson
IPC分类号： G06F9/48
CPC分类号： G06F13/24 , G06F9/30101 , G06F9/3017 , G06F9/30189 , G06F9/3851 , G06F9/461 , G11C7/1072 , G11C11/40615
摘要： In one embodiment, the present invention includes a processor that has an on-die storage such as a static random access memory to store an architectural state of one or more threads that are swapped out of architectural state storage of the processor on entry to a system management mode (SMM). In this way communication of this state information to a system management memory can be avoided, reducing latency associated with entry into SMM. Embodiments may also enable the processor to update a status of executing agents that are either in a long instruction flow or in a system management interrupt (SMI) blocked state, in order to provide an indication to agents inside the SMM. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，本发明包括具有诸如静态随机存取存储器之类的片上存储器的处理器，用于存储在进入系统时从处理器的架构状态存储器交换的一个或多个线程的架构状态 管理模式（SMM）。 以这种方式，可以避免该状态信息与系统管理存储器的通信，减少与进入SMM相关联的延迟。 实施例还可以使处理器更新处于长指令流或处于系统管理中断（SMI）阻塞状态中的执行代理的状态，以向SMM内的代理提供指示。 描述和要求保护其他实施例。
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4.发明申请PROCESSOR THAT DETECTS WHEN SYSTEM MANAGEMENT MODE ATTEMPTS TO REACH PROGRAM CODE OUTSIDE OF PROTECTED SPACE 审中-公开当系统管理模式尝试达到保护空间外的程序代码时，检测器的处理器公开(公告)号：US20130326288A1
公开(公告)日：2013-12-05
申请号：US13997046
申请日：2011-12-31
IPC分类号： G06F11/07
CPC分类号： G06F11/0754 , G06F12/1441 , G06F21/52
摘要： A method is described that includes detecting that a memory access of system management mode program code is attempting to reach program code outside of a protected region of memory by comparing a target memory address of a memory access instruction of the system management program code again information that defines confines of the protection region. The method also includes raising an error signal in response to the detecting.
摘要翻译： 描述了一种方法，其包括通过将系统管理程序代码的存储器访问指令的目标存储器地址再次比较来检测系统管理模式程序代码的存储器访问尝试到达存储器的受保护区域之外的程序代码， 定义保护区域的范围。 该方法还包括响应于检测而提高误差信号。
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5.发明授权Processor that detects when system management mode attempts to reach program code outside of protected space 有权检测系统管理模式何时尝试到达受保护的空间之外的程序代码的处理器公开(公告)号：US09448867B2
公开(公告)日：2016-09-20
申请号：US13997046
申请日：2011-12-31
CPC分类号： G06F11/0754 , G06F12/1441 , G06F21/52
摘要： A method is described that includes detecting that a memory access of system management mode program code is attempting to reach program code outside of a protected region of memory by comparing a target memory address of a memory access instruction of the system management program code again information that defines confines of the protection region. The method also includes raising an error signal in response to the detecting.
摘要翻译： 描述了一种方法，其包括通过将系统管理程序代码的存储器访问指令的目标存储器地址再次比较来检测系统管理模式程序代码的存储器访问尝试到达存储器的受保护区域之外的程序代码， 定义保护区域的范围。 该方法还包括响应于检测而提高误差信号。
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6.发明申请公开(公告)号：US20070277223A1
公开(公告)日：2007-11-29
申请号：US11442230
申请日：2006-05-26
申请人： Shamanna M. Datta , Mohan J. Kumar
发明人： Shamanna M. Datta , Mohan J. Kumar
IPC分类号： H04L9/32
摘要： Methods and apparatus for initiating secure operations in a microprocessor system are described. In one embodiment, a system includes a processor to execute a secured enter instruction, and a chipset to cause the system to enter a quiescent state during execution of the secured enter instruction.
摘要翻译： 描述了在微处理器系统中启动安全操作的方法和装置。 在一个实施例中，系统包括执行安全输入指令的处理器和芯片组，以使系统在执行安全输入指令期间进入静止状态。
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7.发明申请EXECUTION OF A SECURED ENVIRONMENT INITIALIZATION INSTRUCTION ON A POINT-TO-POINT INTERCONNECT SYSTEM 审中-公开一个点到点互连系统的安全环境初始化指导的执行公开(公告)号：US20130212672A1
公开(公告)日：2013-08-15
申请号：US13837498
申请日：2013-03-15
申请人： Shamanna M. Datta , Mohan J. Kumar
发明人： Shamanna M. Datta , Mohan J. Kumar
IPC分类号： G06F21/00
摘要： Methods and apparatus for initiating secure operations in a microprocessor system are described. In one embodiment, a system includes a processor to execute a secured enter instruction, and a chipset to cause the system to enter a quiescent state during execution of the secured enter instruction.
摘要翻译： 描述了在微处理器系统中启动安全操作的方法和装置。 在一个实施例中，系统包括执行安全输入指令的处理器和芯片组，以使系统在执行安全输入指令期间进入静止状态。
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公开(公告)号：US20130212406A1
公开(公告)日：2013-08-15
申请号：US13837640
申请日：2013-03-15
申请人： Shamanna M. Datta , Mohan J. Kumar
发明人： Shamanna M. Datta , Mohan J. Kumar
IPC分类号： G06F21/60
摘要： A technique to verify firmware. One embodiment of the invention uses a processor's micro-code to verify a system's firmware, such that the firmware can be included in a trusted chain of code along with the operating system.
摘要翻译： 验证固件的技术。 本发明的一个实施例使用处理器的微代码来验证系统的固件，使得固件可以与操作系统一起被包括在可信赖的代码链中。
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公开(公告)号：US08429418B2
公开(公告)日：2013-04-23
申请号：US11355697
申请日：2006-02-15
申请人： Shamanna M. Datta , Mohan J. Kumar
发明人： Shamanna M. Datta , Mohan J. Kumar
IPC分类号： G06F21/00
摘要： A technique to verify firmware. One embodiment of the invention uses a processor's micro-code to verify a system's firmware, such that the firmware can be included in a trusted chain of code along with the operating system.
摘要翻译： 验证固件的技术。 本发明的一个实施例使用处理器的微代码来验证系统的固件，使得固件可以与操作系统一起被包括在可信赖的代码链中。
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10.发明申请公开(公告)号：US20140188829A1
公开(公告)日：2014-07-03
申请号：US13728451
申请日：2012-12-27
IPC分类号： G06F17/30
CPC分类号： G06F16/21
摘要： Technologies to generate an error record are described herein. A method includes performing a scan of one or more error logs to identify a source of data in response to an attempt to access the data, determining whether an amount of time to complete the scan will exceed a threshold value, and generating a notice that the error record will be deferred based on the determination. A system includes a data collector to scan one or more error logs to identify a source of data in response to an attempt to access the data, a controller to determine whether an amount of time to scan the error logs to identify the source of data will exceed a threshold value, and a signal generator to generate a signal indicating that the error record is to be deferred based on the determination.
摘要翻译： 本文描述了生成错误记录的技术。 一种方法包括：响应于访问数据的尝试，执行一个或多个错误日志的扫描以识别数据源，确定完成扫描的时间量是否将超过阈值，以及生成通知 错误记录将根据确定推迟。 系统包括数据收集器，用于扫描一个或多个错误日志以响应于访问数据的尝试来识别数据源;控制器，用于确定扫描错误日志以识别数据源的时间量是否将 超过阈值，以及信号发生器，用于基于该确定产生指示错误记录被延迟的信号。
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