公开(公告)号：US07143274B2

公开(公告)日：2006-11-28

申请号：US10674529

申请日：2003-10-01

申请人： Mamoru Sakamoto

发明人： Mamoru Sakamoto

IPC分类号： G06F9/48

CPC分类号： G06F9/4812

摘要： An interrupt controlling method is provided that is capable of executing an interrupt process while avoiding slowing-down in execution speed of a task process. When an interrupt request occurs while a task processing program is being executed, the task processing program is suspended and execution of an interrupt handler is started. By the interrupt handler, a plurality of breakpoints are set in an interrupt process-enabled area (R2). Execution of the resumed task processing program soon reaches one of the plurality of breakpoints. Then, the microprocessor (1) suspends the execution of the task processing program and starts execution of a breakpoint handler. By the breakpoint handler, the interrupt process is executed, and thereafter, the settings of the breakpoints are cleared.

摘要翻译： 提供了能够执行中断处理同时避免任务处理的执行速度变慢的中断控制方法。 当执行任务处理程序时发生中断请求时，暂停任务处理程序并开始中断处理程序的执行。 通过中断处理程序，在中断处理使能区域（R 2）中设置多个断点。 恢复的任务处理程序的执行很快达到多个断点之一。 然后，微处理器（1）暂停执行任务处理程序并开始执行断点处理程序。 通过断点处理程序执行中断处理，此后，断点的设置将被清除。

公开(公告)号：USD288440S

公开(公告)日：1987-02-24

申请号：US621054

申请日：1984-06-15

申请人： Mamoru Sakamoto

设计人： Mamoru Sakamoto

公开(公告)号：US20100259689A1

公开(公告)日：2010-10-14

申请号：US12739551

申请日：2008-10-27

申请人： Masato Tanaka ,  Kazuo Asanuma ,  Mamoru Sakamoto ,  Yasuo Hosaka ,  Akinobu Maekawa ,  Hidehumi Nakagome

发明人： Masato Tanaka ,  Kazuo Asanuma ,  Mamoru Sakamoto ,  Yasuo Hosaka ,  Akinobu Maekawa ,  Hidehumi Nakagome

IPC分类号： H04N9/64

CPC分类号： G09G5/10 ,  G09G3/342 ,  G09G3/3611 ,  G09G5/02 ,  G09G2320/0238 ,  G09G2320/0242 ,  G09G2320/0271 ,  G09G2320/0285 ,  G09G2320/0646 ,  G09G2320/0673 ,  G09G2330/021 ,  G09G2360/16 ,  H04N9/646 ,  H04N9/68 ,  H04N9/73 ,  H04N17/045

摘要： An overflow suppression technique that is effective for avoiding degradation in image quality is provided. A fundamental waveform and detail is extracted out of an input RGB signal. A suppression gain generation unit 614 generates a suppression gain from the extracted fundamental waveform. Multipliers 612a and 612b multiply the detail and the fundamental waveform by the generated suppression gain, respectively. Then, an adder 626 combines them together for a mixed output. Alternatively, equalization processing is performed as follows. A low frequency component fundamental waveform is obtained as a result of the passing of an input RGB signal through a low pass filter 622. A suppression gain is generated from the low frequency component fundamental waveform. Then, the input itself is multiplied by the suppression gain to obtain an output.

摘要翻译： 提供了一种有效避免图像质量下降的溢出抑制技术。 从输入RGB信号中提取基本波形和细节。 抑制增益生成单元614从提取的基本波形生成抑制增益。 乘法器612a和612b将细节和基波分别乘以产生的抑制增益。 然后，加法器626将它们组合在一起用于混合输出。 或者，如下进行均衡处理。 作为输入RGB信号通过低通滤波器622的结果，获得低频分量基波。由低频分量基波形成产生抑制增益。 然后，输入本身乘以抑制增益以获得输出。

公开(公告)号：US20060132059A1

公开(公告)日：2006-06-22

申请号：US11198486

申请日：2005-08-05

申请人： Masato Tanaka ,  Yasuo Hosaka ,  Mamoru Sakamoto ,  Akinobu Maekawa ,  Hidefumi Nakagome

发明人： Masato Tanaka ,  Yasuo Hosaka ,  Mamoru Sakamoto ,  Akinobu Maekawa ,  Hidefumi Nakagome

IPC分类号： H05B41/16

CPC分类号： H05B41/282 ,  Y02B20/183

摘要： The present invention relates to a lamp lighting technique for lighting multiple lamps safely without luminance irregularities. The present lamp lighting circuit includes multiple closed loops wherein a predetermined number of lamps and the secondary windings of the predetermined number of transformers are connected serially. At least one of the primary windings of the transformers employed for each closed loop is connected to the primary winding of the transformer employed for another closed loop serially. Thus, current of the lamps included in the closed loop is made uniform, and also current is made uniform even between the closed loops by connecting the primary windings of the transformers serially. According to the present invention, with regard to serial connection of the primary windings of the transformers, even if the number of transformers is limited, current uniformity can be propagated to the entirety by subjecting closed loops to catenation consecutively.

摘要翻译： 本发明涉及安全地照明多个灯而不发生亮度不均匀的灯照明技术。 本灯点亮电路包括多个闭环，其中预定数量的灯和预定数量的变压器的次级绕组串联连接。 用于每个闭环的变压器的初级绕组中的至少一个连接到用于另一个闭环的变压器的初级绕组。 因此，包含在闭环中的灯的电流被均匀化，并且即使在闭环之间通过串联连接变压器的初级绕组也使电流均匀。 根据本发明，关于变压器的初级绕组的串联连接，即使变压器的数量受到限制，电流均匀性可以通过使闭环连续地连接而传播到整体。

公开(公告)号：US20120076418A1

公开(公告)日：2012-03-29

申请号：US13186866

申请日：2011-07-20

申请人： Yukiyoshi SASAO ,  Mamoru Sakamoto

发明人： Yukiyoshi SASAO ,  Mamoru Sakamoto

IPC分类号： G06K9/46

CPC分类号： G06K9/00308

摘要： To provide a face attribute estimating apparatus capable of determining a face attribute with high precision. A scan region extracting part extracts, as a scan region, a region in which a specific face part can exist from a face region detected by a face detecting part. A region scanning part sets a small region in the scan region extracted by the scan region extracting part and, while scanning the scan region with the small region, sequentially outputs a pixel value in the small region. A pattern similarity calculating part sequentially calculates similarity between the pixel value output from the region scanning part and a specific pattern on the specific face part. A face attribute determining part determines a face attribute by comprehensively determining the similarities sequentially calculated by the pattern similarity calculating part. Therefore, a face attribute can be determined with high precision.

摘要翻译： 提供能够高精度地确定面部属性的面部属性估计装置。 扫描区域提取部分从脸部检测部分检测到的面部区域中提取特定面部部分可以存在的区域作为扫描区域。 区域扫描部分设置由扫描区域提取部分提取的扫描区域中的小区域，并且在扫描具有小区域的扫描区域的同时，顺序地输出小区域中的像素值。 模式相似度计算部分顺序地计算从区域扫描部分输出的像素值与特定脸部部分上的特定图案之间的相似度。 面部属性确定部分通过综合确定由模式相似度计算部分顺序计算的相似度来确定面部属性。 因此，可以高精度地确定脸部属性。

公开(公告)号：US06958593B2

公开(公告)日：2005-10-25

申请号：US10698434

申请日：2003-11-03

申请人： Kazuo Asanuma ,  Mamoru Sakamoto

发明人： Kazuo Asanuma ,  Mamoru Sakamoto

IPC分类号： H02M3/155 ,  G05F1/46 ,  G05F1/44

CPC分类号： G05F1/46

摘要： This invention provides a stable power supply apparatus enabling the high speed response. Hitherto, it was necessary to secure both of the gain margin and the phase margin on the Bode diagram of the loop transfer function when the PID feedback control was carried out in the power supply apparatus. The form of the transfer function of the controller in the power supply apparatus of this invention is the same, but a set of coefficient values in the transfer function is completely different, and the controller secures only the phase margin without securing the gain margin. Furthermore, the transfer function of the controller indicates a part with an extreme decrease in the gain and a trap point in which the phase is sharply delayed on the Bode diagram. This is achieved by applying the integral element of the PID to a frequency range that is higher than the resonance frequency of the LC filter. As a result, the high speed response becomes possible without losing the stability. Moreover, there is no case in which difficulty as to the setting of the circuit constants rises.

摘要翻译： 本发明提供一种能够实现高速响应的稳定的电源装置。 到目前为止，当在电源装置中进行PID反馈控制时，有必要确保环路传递函数的波德图的增益裕度和相位裕度。 本发明的电源装置中的控制器的传递函数的形式是相同的，但是传递函数中的一组系数值完全不同，并且控制器仅确保相位裕度，而不保证增益裕度。 此外，控制器的传递函数指示增益极度下降的部分和波德图上相位急剧延迟的陷阱点。 这通过将PID的积分元件应用于高于LC滤波器的谐振频率的频率范围来实现。 结果，高速响应成为可能，而不失去稳定性。 此外，不存在电路常数的设定困难上升的情况。

公开(公告)号：US06279079B1

公开(公告)日：2001-08-21

申请号：US09440933

申请日：1999-11-16

申请人： Mamoru Sakamoto

发明人： Mamoru Sakamoto

IPC分类号： G06F1200

CPC分类号： G06F12/12 ,  G06F12/0875

摘要： A duplicate of a function code is created in a fast memory contiguous with a normal memory so that a CPU checks whether the duplicate is located in the fast memory when the function code is called; and a block containing a function code may be released so as to create therein a duplicate of a new function code.

摘要翻译： 在与正常存储器相连的快速存储器中创建功能代码的副本，以便当调用功能代码时，CPU检查副本是否位于快速存储器中; 并且可以释放包含功能代码的块，以便在其中创建新的功能代码的副本。

公开(公告)号：US07408306B2

公开(公告)日：2008-08-05

申请号：US11198486

申请日：2005-08-05

申请人： Masato Tanaka ,  Yasuo Hosaka ,  Mamoru Sakamoto ,  Akinobu Maekawa ,  Hidefumi Nakagome

发明人： Masato Tanaka ,  Yasuo Hosaka ,  Mamoru Sakamoto ,  Akinobu Maekawa ,  Hidefumi Nakagome

IPC分类号： H05B41/24

CPC分类号： H05B41/282 ,  Y02B20/183

摘要： The present invention relates to a lamp lighting technique for lighting multiple lamps safely without luminance irregularities. The present lamp lighting circuit includes multiple closed loops wherein a predetermined number of lamps and the secondary windings of the predetermined number of transformers are connected serially. At least one of the primary windings of the transformers employed for each closed loop is connected to the primary winding of the transformer employed for another closed loop serially. Thus, current of the lamps included in the closed loop is made uniform, and also current is made uniform even between the closed loops by connecting the primary windings of the transformers serially. According to the present invention, with regard to serial connection of the primary windings of the transformers, even if the number of transformers is limited, current uniformity can be propagated to the entirety by subjecting closed loops to catenation consecutively.

摘要翻译： 本发明涉及安全地照明多个灯而不发生亮度不均匀的灯照明技术。 本灯点亮电路包括多个闭环，其中预定数量的灯和预定数量的变压器的次级绕组串联连接。 用于每个闭环的变压器的初级绕组中的至少一个连接到用于另一个闭环的变压器的初级绕组。 因此，包含在闭环中的灯的电流被均匀化，并且即使在闭环之间通过串联连接变压器的初级绕组也使电流均匀。 根据本发明，关于变压器的初级绕组的串联连接，即使变压器的数量受到限制，电流均匀性可以通过使闭环连续地连接而传播到整体。

公开(公告)号：US06871259B2

公开(公告)日：2005-03-22

申请号：US10166636

申请日：2002-06-12

申请人： Masato Hagiwara ,  Mamoru Sakamoto

发明人： Masato Hagiwara ,  Mamoru Sakamoto

IPC分类号： G06F12/16 ,  G06F12/00 ,  G06F12/02

CPC分类号： G06F12/0246

摘要： A flash memory includes a data bank having a plurality of banks, a merge bank, and an update data bank. A file system using the flash memory includes a unit storing update data corresponding to a data rewrite command into the update data bank, a unit selecting the latest update data for each block from update data stored in the update data bank when the update data bank becomes full, and a processing unit processing the latest update data. The processing unit includes a unit storing latest update data into a merge bank, a unit selecting data associated with the latest update data from the data bank to store the selected data into the merge bank, and a unit setting the merge bank as a new data bank.

摘要翻译： 闪速存储器包括具有多个存储体的数据库，合并存储体和更新数据存储体。 使用闪速存储器的文件系统包括将对应于数据重写命令的更新数据存储到更新数据库中的单元，当更新数据库变为（或更新数据库）时，从存储在更新数据库中的更新数据中选择每个块的最新更新数据的单元 并且处理单元处理最新的更新数据。 处理单元包括将最新更新数据存储到合并库中的单元，从数据库选择与最新更新数据相关联的数据以将选择的数据存储到合并库中的单元，以及将合并库设置为新数据的单元 银行。

公开(公告)号：US06820252B2

公开(公告)日：2004-11-16

申请号：US09995837

申请日：2001-11-29

申请人： Mamoru Sakamoto ,  Toyohiko Yoshida

发明人： Mamoru Sakamoto ,  Toyohiko Yoshida

IPC分类号： G06F945

CPC分类号： G06F9/30174 ,  G06F9/45504

摘要： A data processor includes a hardware translator converting non-native code into a native code to a processor, a software translator converting non-native code into a native code to the processor by software, and a software interpreter sequentially interpreting a code that is non-native to the processor, and executing the interpreted code using a native code of the processor. The data processor includes a circuit selecting the hardware translator, software translator or software interpreter according to a predetermined criterion for operation.

摘要翻译： 数据处理器包括将非本机代码转换成本地代码到处理器的硬件翻译器，通过软件将非本地代码转换为本地代码到处理器的软件翻译器，以及顺序地解释非代码代码的软件解释器， 并且使用处理器的本地代码来执行解释的代码。 数据处理器包括根据预定的操作标准选择硬件翻译器，软件翻译器或软件解释器的电路。