公开(公告)号：US06807623B2

公开(公告)日：2004-10-19

申请号：US09916050

申请日：2001-07-26

申请人： Manabu Migita ,  Junji Nishikawa ,  Ichiro Okabayashi ,  Shinji Furuya

发明人： Manabu Migita ,  Junji Nishikawa ,  Ichiro Okabayashi ,  Shinji Furuya

IPC分类号： G06F1100

CPC分类号： G06F9/52 ,  G06F3/0613 ,  G06F3/0659 ,  G06F3/0689 ,  G06F9/4843 ,  G06F9/5011

摘要： A data processing control system has a controller wherein the controller (1) sends every received instruction to the plurality of data processing devices until the number of instructions being executed or waiting to be executed by the plurality of data processing devices reaches a predetermined number, (2) does not send any received instructions to the plurality of data processing devices but holds the received instructions in a queue once the number of instructions being executed or waiting to be executed by the plurality of data processing devices has reached the predetermined number, and (3) when the number of instructions being executed or waiting to be executed by the plurality of data processing devices has become zero by completing the execution thereof, starts sending the queued instructions in sequence to the plurality of data processing devices, and continues to send the queued instructions or every newly received instruction to the plurality of data processing devices until the number of instructions being executed or waiting to be executed by the plurality of data processing devices reaches the predetermined number.

摘要翻译： 数据处理控制系统具有控制器，其中控制器（1）将每个接收到的指令发送到多个数据处理设备，直到被多个数据处理设备执行或等待执行的指令的数量达到预定数量（ 一旦所执行的等待执行的指令的数目已经达到预定数量，并且（2）不向所述多个数据处理装置发送任何接收的指令，而是将所接收的指令保持在队列中，并且 3）当由多个数据处理装置执行或等待执行的指令数量通过完成其执行而变为零时，开始按顺序向多个数据处理装置发送排队的指令，并且继续发送 排队的指令或每个新接收的指令到多个数据处理设备，直到 正在执行或等待由多个数据处理装置执行的指令的数量达到预定数量。

公开(公告)号：US06735672B2

公开(公告)日：2004-05-11

申请号：US09965778

申请日：2001-09-29

申请人： Junji Nishikawa ,  Manabu Migita

发明人： Junji Nishikawa ,  Manabu Migita

IPC分类号： G06F1200

CPC分类号： G06F11/1088 ,  G06F3/0611 ,  G06F3/0659 ,  G06F3/0689 ,  G06F11/1076 ,  G06F2211/1016 ,  H04N7/17336 ,  H04N21/2312 ,  H04N21/2326 ,  H04N21/2396

摘要： A data storage array device includes redundant data storage devices and a controller. The controller includes a set of instructions issued to the data storage devices; a detector for detecting responses to the set of instructions; a timer; and a processor for monitoring the responses. If the responses from all data storage devices finished within a period set by the timer, the processor completes response processing for the set of instructions at the point when the responses finished. If the responses from all data storage devices are not finished at the end of a period set by the timer, the processor completes response processing for the set of instructions using only the responses that are finished at the end of the period of the timer.

摘要翻译： 数据存储阵列装置包括冗余数据存储装置和控制器。 该控制器包括一组发给数据存储设备的指令; 用于检测对所述一组指令的响应的检测器; 一个计时器 以及用于监视响应的处理器。 如果来自所有数据存储设备的响应在由定时器设置的时段内完成，则处理器在响应完成时完成对该组指令的响应处理。 如果来自所有数据存储设备的响应在由定时器设置的周期结束时未完成，则处理器仅使用在定时器的周期结束时完成的响应来完成该组指令的响应处理。

公开(公告)号：US5928339A

公开(公告)日：1999-07-27

申请号：US954694

申请日：1997-10-20

申请人： Junji Nishikawa

发明人： Junji Nishikawa

IPC分类号： G06F13/28 ,  G06F13/10 ,  G06F13/374 ,  G06F13/38

CPC分类号： G06F13/28

摘要： A data transfer apparatus for DMA-transferring stream data between a memory and each of n ports. The data transfer apparatus includes: an address counter for storing a start address of a memory area between which and a port a next piece of stream data is DMA-transferred; a data counter for storing a size of the next piece of stream data; n chain address counters each for storing an address of a memory area storing a certain command list; a port selecting unit for selecting one port; a command list transferring unit for, each time the port selecting unit selects a port, obtaining a command list according to a chain address counter corresponding to the selected port, transferring a start address in the command list to the address counter, transferring a size in the command list to the data counter, transferring the command to the port selecting unit, and updates the chain address counter; a stream data transferring unit for DMA-transferring a piece of stream data between the selected port and the memory area specified by the address counter. After the stream data transferring unit completes a DMA transfer, the port selecting unit, based on a predetermined order and the command, selects a new port or a current port. Each time the command list transferring unit transfers the size to the data counter, the stream data transferring unit DMA-transfers a piece of stream data between the selected port and the memory area specified by the address counter.

摘要翻译： 一种用于在存储器和n个端口中的每一个之间DMA流传输数据的数据传送装置。 数据传送装置包括：地址计数器，用于存储其中与下一个数据流数据的端口DMA传送的存储区域的起始地址; 用于存储下一条流数据的大小的数据计数器; n个链路地址计数器，用于存储存储特定命令列表的存储区域的地址; 用于选择一个端口的端口选择单元; 命令列表传送单元，用于每当端口选择单元选择端口时，根据与所选择的端口相对应的链地址计数器获取命令列表，将命令列表中的起始地址传送到地址计数器， 将命令列表发送到数据计数器，将命令传送到端口选择单元，并更新链地址计数器; 流数据传送单元，用于在所选择的端口和由地址计数器指定的存储区之间DMA传输流数据。 在流数据传送单元完成DMA传输之后，端口选择单元基于预定顺序和命令，选择新端口或当前端口。 每当命令列表传送单元将大小传送到数据计数器时，流数据传送单元DMA在所选择的端口和由地址计数器指定的存储区之间传送一条流数据。

公开(公告)号：US5526490A

公开(公告)日：1996-06-11

申请号：US104583

申请日：1993-08-11

申请人： Junji Nishikawa

发明人： Junji Nishikawa

IPC分类号： G06F13/12 ,  G06F15/163

CPC分类号： G06F13/122

摘要： A processor element is provided with a data transfer control circuit that sends out an address count pulse (ACNT) onto a control bus. N data transfer channels each contain a data transfer buffer and a buffer control circuit. The buffer control circuit comprises an identification number register, an input/output control circuit, an address counter, and a comparison circuit. The address counter holds a channel address that is preset in such a way as to allow each channel to take the same channel address number, and increments such a channel address each time it receives the ACNT. If the identification number and the channel address coincide, the data transfer buffer in the same channel is selected. The number of interconnecting wires can be reduced and the transfer of data can be carried out at a high transfer rate, in a multiprocessor system whose linking network between each processor is formed by a series of data transfer channels.

摘要翻译： 处理器元件设置有将地址计数脉冲（ACNT）发送到控制总线上的数据传输控制电路。 N个数据传送通道各自包含数据传送缓冲器和缓冲器控制电路。 缓冲器控制电路包括识别号寄存器，输入/输出控制电路，地址计数器和比较电路。 地址计数器保持以允许每个通道采用相同的通道地址号码的方式预先设置的通道地址，并且每当接收到ACNT时增加这样的通道地址。 如果识别号和通道地址一致，则选择同一通道中的数据传输缓冲器。 在多处理器系统中，可以以高传输速率来实现互连线的数量，并且数据传输可以通过一系列数据传输通道形成每个处理器之间的链接网络的多处理器系统。

公开(公告)号：US5488852A

公开(公告)日：1996-02-06

申请号：US262448

申请日：1994-06-20

申请人： Junji Nishikawa ,  Ryoichi Yamada

发明人： Junji Nishikawa ,  Ryoichi Yamada

IPC分类号： B21K27/00 ,  B21D43/05 ,  B21K27/04

CPC分类号： B21K27/04

摘要： A transfer feeder for hot-forging presses having a clamping mechanism to move two parallel feed bars in the clamp and unclamp directions, an advancing mechanism to move them in the advance and return directions, and a lifting mechanism to raise and lower them. The two feed bars are connected to an inner frame via a pair of parallel links and a pair of supporting links, the inner frame is rockably supported on an intermediate frame in the advance and return directions, the intermediate frame is supported on the outer frame to be freely raised and lowered in relation to the outer frame, the clamping mechanism is so constructed as to rock parallel links in the clamp and unclamp directions, the advancing mechanism is so constructed as to rock the inner frame in relation to the intermediate frame, and the lifting mechanism is so constructed as to raise and lower the intermediate frame in relation to the outer frame. The advantages are that the clamping mechanism is perfectly synchronized and, if the central segment of a feed bar is removed, end segments will not hang down.

摘要翻译： 一种用于热锻压机的转送给料机，具有夹紧机构，用于使夹紧器和松开方向上的两个平行进给杆移动，使前进机构沿前后方向移动的推进机构和升降机构。 两个进给杆经由一对平行连杆和一对支撑连接件连接到内框架上，内框架以提前和返回方向可摆动地支撑在中间框架上，中间框架支撑在外框架上 相对于外框架自由地升高和降低，夹紧机构被构造成在夹具和松开方向上摇动平行连杆，推进机构构造成相对于中间框架摇动内框架，并且 升降机构被构造为相对于外框架升高和降低中间框架。 优点是夹紧机构是完全同步的，并且如果进给杆的中心部分被去除，则端部段将不会下垂。

公开(公告)号：US5842035A

公开(公告)日：1998-11-24

申请号：US410077

申请日：1995-03-24

申请人： Junji Nishikawa

发明人： Junji Nishikawa

IPC分类号： G06F15/16 ,  G06F15/177 ,  G06F15/80

CPC分类号： G06F15/8007

摘要： A parallel computer comprising a plurality of processor elements and a network interconnecting the same, wherein each of the plurality of processor elements includes: a memory unit including a first area and a second area, the first area storing a program and a data portion allocated to the processor element, the second area having a smaller capacity than the first area and storing working data temporarily; a first data transferring unit for performing a first data transfer, whereby data necessary for an operation are transferred to the second area from the first areas of the other processor elements via the network to form a new data portion therein; a processor for performing a first operation, whereby the data portion in the first area is processed as per program and an operation result is restored into the first area, and for performing a second operation, whereby the new data portion in the second area is processed as per program and an operation result is restored into the second area; and a second data transferring unit for performing a second data transfer, whereby the operation results restored in the second areas in the other processor elements are transferred to the first area of the processor element via the network.

摘要翻译： 一种并行计算机，包括多个处理器元件和互连其的网络，其中所述多个处理器元件中的每一个包括：包括第一区域和第二区域的存储器单元，所述第一区域存储程序和分配给 所述处理器元件，所述第二区域具有比所述第一区域更小的容量并且临时存储工作数据; 用于执行第一数据传送的第一数据传送单元，由此操​​作所需的数据经由网络从其他处理器单元的第一区域传送到第二区域，以在其中形成新的数据部分; 用于执行第一操作的处理器，由此根据程序处理第一区域中的数据部分，并且将操作结果恢复到第一区域中，并且用于执行第二操作，由此处理第二区域中的新数据部分 根据程序，操作结果恢复到第二区域; 以及第二数据传送单元，用于执行第二数据传送，由此在其他处理器元件中的第二区域中恢复的操作结果经由网络被传送到处理器元件的第一区域。

公开(公告)号：US5513364A

公开(公告)日：1996-04-30

申请号：US205417

申请日：1994-03-03

申请人： Junji Nishikawa

发明人： Junji Nishikawa

IPC分类号： G06F13/40 ,  G06F13/00

CPC分类号： G06F13/4022

摘要： In a data transfer control device for controlling a data transfer bus connected to plural buffer units, an address generation circuit for specifying a buffer unit address is provided with an address register for holding upper and lower limit values of the buffer unit address, an address counter which sequentially increments the buffer unit address, starting from the lower limit value, and a comparator for judging whether an output of the address counter reaches to the upper limit value. The data transfer control device composes a crossbar-type data transfer network together with the buffer units, and plural processor elements or plural I/O devices are connected to the network.

摘要翻译： 在用于控制连接到多个缓冲单元的数据传输总线的数据传输控制装置中，用于指定缓冲单元地址的地址生成电路设置有用于保存缓冲单元地址的上限和下限值的地址寄存器，地址计数器 其从下限值开始顺序地增加缓冲器单元地址，以及用于判断地址计数器的输出是否达到上限值的比较器。 数据传输控制装置与缓冲单元一起构成交叉式数据传送网络，并且多个处理器单元或多个I / O设备连接到网络。

公开(公告)号：US5295381A

公开(公告)日：1994-03-22

申请号：US959585

申请日：1992-10-13

申请人： Junji Nishikawa ,  Hiromichi Konishi ,  Masashi Tado ,  Yasumasa Sato

发明人： Junji Nishikawa ,  Hiromichi Konishi ,  Masashi Tado ,  Yasumasa Sato

IPC分类号： B21D11/16 ,  B21K1/08

CPC分类号： B21K1/08 ,  B21D11/16 ,  Y10T29/17

摘要： A twist-forming process and a coining process for a crank shaft are carried out by using one twist-forming press including a twist forming section and a coining section, and a stopper height adjusting means for determining the crank pin arrangement and for finely adjusting the twist angles is integrally incorporated into the twist-forming press.

摘要翻译： 用于曲轴的扭曲成形过程和压印过程通过使用包括扭转形成部分和压印部分的一个扭曲成型压力机和用于确定曲柄销装置并用于精细调节 扭转角度一体地结合到扭曲成型压机中。