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    Conditional and vectored system management interrupts
    1.
    发明申请
    Conditional and vectored system management interrupts 有权
    有条件和向量的系统管理中断

    公开(公告)号：US20070150632A1

    公开(公告)日：2007-06-28

    申请号：US11320923

    申请日：2005-12-28

    申请人： Mani Ayyar ,  Ioannis Schoinas ,  Rama Menon ,  Aniruddha Vaidya ,  Akhilesh Kumar

    发明人： Mani Ayyar ,  Ioannis Schoinas ,  Rama Menon ,  Aniruddha Vaidya ,  Akhilesh Kumar

    IPC分类号： G06F13/24

    CPC分类号： G06F13/24

    摘要： An embodiment of the present invention is a technique to process system management interrupt. A system management interrupt (SMI) is received. The SMI is associated with a system management mode (SMM). A conditional SMI inter-processor interrupt (IPI) message is broadcast to at least a processor. The SMI is processed without waiting for the at least processor to check into the SMM. A clear pending SMI is broadcast to the processors at end of SMI processing to clear a pending SMI condition.

    摘要翻译： 本发明的一个实施例是一种处理系统管理中断的技术。 系统管理中断（SMI）被接收。 SMI与系统管理模式（SMM）相关联。 至少处理器广播条件SMI处理器间中断（IPI）消息。 在不等待至少处理器检查SMM的情况下处理SMI。 在SMI处理结束时将清除待处理的SMI广播到处理器，以清除待处理的SMI条件。

    Conditional and vectored system management interrupts
    2.
    发明授权
    Conditional and vectored system management interrupts 有权
    有条件和向量的系统管理中断

    公开(公告)号：US07433985B2

    公开(公告)日：2008-10-07

    申请号：US11320923

    申请日：2005-12-28

    申请人： Mani Ayyar ,  Ioannis Schoinas ,  Rama R. Menon ,  Aniruddha Vaidya ,  Akhilesh Kumar

    发明人： Mani Ayyar ,  Ioannis Schoinas ,  Rama R. Menon ,  Aniruddha Vaidya ,  Akhilesh Kumar

    IPC分类号： G06F13/24 ,  G06F13/26 ,  G06F13/32

    CPC分类号： G06F13/24

    摘要： An embodiment of the present invention is a technique to process system management interrupt. A system management interrupt (SMI) is received. The SMI is associated with a system management mode (SMM). A conditional SMI inter-processor interrupt (IPI) message is broadcast to at least a processor. The SMI is processed without waiting for the at least processor to check into the SMM. A clear pending SMI is broadcast to the processors at end of SMI processing to clear a pending SMI condition.

    摘要翻译： 本发明的一个实施例是一种处理系统管理中断的技术。 系统管理中断（SMI）被接收。 SMI与系统管理模式（SMM）相关联。 至少处理器广播条件SMI处理器间中断（IPI）消息。 在不等待至少处理器检查SMM的情况下处理SMI。 在SMI处理结束时将清除待处理的SMI广播到处理器，以清除待处理的SMI条件。

    Method, System, and Apparatus for System Level Initialization
    4.
    发明申请
    Method, System, and Apparatus for System Level Initialization 有权
    用于系统级初始化的方法，系统和装置

    公开(公告)号：US20090265472A1

    公开(公告)日：2009-10-22

    申请号：US12348723

    申请日：2009-01-05

    申请人： Mani Ayyar ,  Srinivas Chennupaty ,  Akhilesh Kumar ,  Doddabaliapur Narasimha-Murthy Jayasimha ,  Murugasamy Nachimuthu ,  Phanindra K. Mannava ,  Ioannis T. Schoinas

    发明人： Mani Ayyar ,  Srinivas Chennupaty ,  Akhilesh Kumar ,  Doddabaliapur Narasimha-Murthy Jayasimha ,  Murugasamy Nachimuthu ,  Phanindra K. Mannava ,  Ioannis T. Schoinas

    IPC分类号： G06F15/16 ,  G06F15/177

    CPC分类号： H04L67/125 ,  H04L69/324

    摘要： Multiple initialization techniques for system and component in a point-to-point architecture are discussed. Consequently, the techniques allow for flexible system/socket layer parameters to be tailored to the needs of the platform, such as, desktop, mobile, small server, large server, etc., as well as the component types such as IA32/IPF processors, memory controllers, IO Hubs, etc. Furthermore, the techniques facilitate powering up with the correct set of POC values, hence, it avoids multiple warm resets and improves boot time. In one embodiment, registers to hold new values, such as, Configuration Values Driven during Reset (CVDR), and Configuration Values Captured during Reset (CVCR) may be eliminated.For example, the POC values could be from the following: Platform Input Clock to Core Clock Ratio, Enable/disable LT, Configurable Restart, Burn In Initialization Mode, Disable Hyper Threading, System BSP Socket Indication, and Platform Topology Index.

    摘要翻译： 讨论了用于系统和组件在点对点架构中的多个初始化技术。 因此，这些技术允许根据平台（如桌面，移动，小型服务器，大型服务器等）的需求以及诸如IA32 / IPF处理器之类的组件类型来定制灵活的系统/套接字层参数 ，存储器控制器，IO集线器等。此外，该技术有助于以正确的一组POC值加电，因此避免了多次热复位并提高了启动时间。 在一个实施例中，可以消除保存新值的寄存器，例如在复位期间驱动的配置值（CVDR）和在复位期间捕获的配置值（CVCR）。 例如，POC值可以来自以下内容：平台输入时钟到核心时钟比率，启用/禁用LT，可配置重新启动，刻录初始化模式，禁用超线程，系统BSP插槽指示和平台拓扑索引。

    Method, system, and apparatus for system level initialization by conveying capabilities and identifiers of components
    6.
    发明授权
    Method, system, and apparatus for system level initialization by conveying capabilities and identifiers of components 有权
    通过传送组件的功能和标识符来进行系统级初始化的方法，系统和装置

    公开(公告)号：US08606934B2

    公开(公告)日：2013-12-10

    申请号：US12348723

    申请日：2009-01-05

    申请人： Mani Ayyar ,  Srinivas Chennupaty ,  Akhilesh Kumar ,  Doddabaliapur Narasimha-Murthy Jayasimha ,  Murugasamy Nachimuthu ,  Phanindra K. Mannava ,  Ioannis T. Schoinas

    发明人： Mani Ayyar ,  Srinivas Chennupaty ,  Akhilesh Kumar ,  Doddabaliapur Narasimha-Murthy Jayasimha ,  Murugasamy Nachimuthu ,  Phanindra K. Mannava ,  Ioannis T. Schoinas

    IPC分类号： G06F3/00 ,  G06F13/00 ,  G06F15/16 ,  G06F15/177 ,  H04L12/42

    CPC分类号： H04L67/125 ,  H04L69/324

    摘要： Multiple initialization techniques for system and component in a point-to-point architecture are discussed. Consequently, the techniques allow for flexible system/socket layer parameters to be tailored to the needs of the platform, such as, desktop, mobile, small server, large server, etc., as well as the component types such as IA32/IPF processors, memory controllers, IO Hubs, etc. Furthermore, the techniques facilitate powering up with the correct set of POC values, hence, it avoids multiple warm resets and improves boot time. In one embodiment, registers to hold new values, such as, Configuration Values Driven during Reset (CVDR), and Configuration Values Captured during Reset (CVCR) may be eliminated.For example, the POC values could be from the following: Platform Input Clock to Core Clock Ratio, Enable/disable LT, Configurable Restart, Burn In Initialization Mode, Disable Hyper Threading, System BSP Socket Indication, and Platform Topology Index.

    摘要翻译： 讨论了用于系统和组件在点对点架构中的多个初始化技术。 因此，这些技术允许根据平台（如桌面，移动，小型服务器，大型服务器等）的需求以及诸如IA32 / IPF处理器之类的组件类型来定制灵活的系统/套接字层参数 ，存储器控制器，IO集线器等。此外，该技术有助于以正确的一组POC值加电，因此避免了多次热复位并提高了启动时间。 在一个实施例中，可以消除保存新值的寄存器，例如在复位期间驱动的配置值（CVDR）和在复位期间捕获的配置值（CVCR）。 例如，POC值可以来自以下内容：平台输入时钟到核心时钟比率，启用/禁用LT，可配置重新启动，刻录初始化模式，禁用超线程，系统BSP插槽指示和平台拓扑索引。

    Method, system, and apparatus for dynamic reconfiguration of resources
    8.
    发明授权
    Method, system, and apparatus for dynamic reconfiguration of resources 有权
    用于动态重新配置资源的方法，系统和装置

    公开(公告)号：US08171121B2

    公开(公告)日：2012-05-01

    申请号：US12236047

    申请日：2008-09-23

    申请人： Mani Ayyar ,  Eric Delano ,  Ioannis T. Schoinas ,  Akhilesh Kumar ,  Jay Jayasimha ,  Jose A. Vargas

    发明人： Mani Ayyar ,  Eric Delano ,  Ioannis T. Schoinas ,  Akhilesh Kumar ,  Jay Jayasimha ,  Jose A. Vargas

    IPC分类号： G06F15/177 ,  G06F15/76

    CPC分类号： G06F9/44505 ,  G06F9/50 ,  G06F9/5011 ,  G06F13/00 ,  G06F13/24 ,  G06F13/4081 ,  G06F13/409

    摘要： A dynamic reconfiguration to include on-line addition, deletion, and replacement of individual modules of to support dynamic partitioning of a system, interconnect (link) reconfiguration, memory RAS to allow migration and mirroring without OS intervention, dynamic memory reinterleaving, CPU and socket migration, and support for global shared memory across partitions is described. To facilitate the on-line addition or deletion, the firmware is able to quiesce and de-quiesce the domain of interest so that many system resources, such as routing tables and address decoders, can be updated in what essentially appears to be an atomic operation to the software layer above the firmware.

    摘要翻译： 动态重新配置，包括单独模块的在线添加，删除和替换，以支持系统的动态分区，互连（链接）重新配置，存储器RAS以允许无OS干预的迁移和镜像，动态内存重新交织，CPU和插座 描述了跨分区的全局共享内存的迁移和支持。 为了便于在线添加或删除，固件能够静默和解除感兴趣的域，以便许多系统资源（如路由表和地址解码器）可以在基本上看起来是原子操作 到固件上方的软件层。

    Method, system, and apparatus for system level initialization
    9.
    发明申请
    Method, system, and apparatus for system level initialization 有权
    用于系统级初始化的方法，系统和装置

    公开(公告)号：US20060126656A1

    公开(公告)日：2006-06-15

    申请号：US11011801

    申请日：2004-12-13

    申请人： Mani Ayyar ,  Srinivas Chennupaty ,  Akhilesh Kumar ,  Doddaballapur Jayasimha ,  Murugasamy Nachimuthu ,  Phanindra Mannava

    发明人： Mani Ayyar ,  Srinivas Chennupaty ,  Akhilesh Kumar ,  Doddaballapur Jayasimha ,  Murugasamy Nachimuthu ,  Phanindra Mannava

    IPC分类号： H04L12/42

    CPC分类号： H04L67/125 ,  H04L69/324

    摘要： Multiple initialization techniques for system and component in a point-to-point architecture are discussed. Consequently, the techniques allow for flexible system/socket layer parameters to be tailored to the needs of the platform, such as, desktop, mobile, small server, large server, etc., as well as the component types such as IA32/IPF processors, memory controllers, IO Hubs, etc. Furthermore, the techniques facilitate powering up with the correct set of POC values, hence, it avoids multiple warm resets and improves boot time. In one embodiment, registers to hold new values, such as, Configuration Values Driven during Reset (CVDR), and Configuration Values Captured during Reset (CVCR) may be eliminated. For example, the POC values could be from the following: Platform Input Clock to Core Clock Ratio, Enable/disable LT, Configurable Restart, Burn In Initialization Mode, Disable Hyper Threading, System BSP Socket Indication, and Platform Topology Index.

    摘要翻译： 讨论了用于系统和组件在点对点架构中的多个初始化技术。 因此，这些技术允许根据平台（如桌面，移动，小型服务器，大型服务器等）的需求以及诸如IA32 / IPF处理器之类的组件类型来定制灵活的系统/套接字层参数 ，存储器控制器，IO集线器等。此外，该技术有助于以正确的一组POC值加电，因此避免了多次热复位并提高了启动时间。 在一个实施例中，可以消除保存新值的寄存器，例如在复位期间驱动的配置值（CVDR）和在复位期间捕获的配置值（CVCR）。 例如，POC值可以来自以下内容：平台输入时钟到核心时钟比率，启用/禁用LT，可配置重新启动，刻录初始化模式，禁用超线程，系统BSP插槽指示和平台拓扑索引。