Protocol for conflicting memory transactions
    1.
    发明授权
    Protocol for conflicting memory transactions 有权
    内存交易冲突的协议

    公开(公告)号:US09235520B2

    公开(公告)日:2016-01-12

    申请号:US13997900

    申请日:2011-12-20

    摘要: Embodiments of the invention describe a cache coherency protocol that eliminates the need for ordering between message classes and also eliminates home tracker preallocation. Embodiments of the invention describe a less complex conflict detection and resolution mechanism (at the home agent) without any performance degradation in form of bandwidth or latency compared to prior art solutions.Embodiments of the invention describe a home agent that may receive request messages, e.g., data ownership request messages and data request messages, which include issuance data indicating an order of the respective message issued. Said home agent may determine whether an early or late conflict exists based, at least in part, on a received conflict response message and the issuance data of a most recent completed transaction.

    摘要翻译: 本发明的实施例描述了高速缓存一致性协议,其消除了在消息类之间排序的需要,并且还消除了家庭跟踪器预分配。 与现有技术的解决方案相比,本发明的实施例描述了一种不太复杂的冲突检测和解决机制(在归属代理),与带宽或延迟形式没有任何性能下降。 本发明的实施例描述了可以接收诸如数据所有权请求消息和数据请求消息的请求消息的归属代理,其包括指示所发出的各个消息的顺序的发布数据。 所述归属代理可以至少部分地基于接收到的冲突响应消息和最近完成的交易的发行数据来确定是否存在早期或晚期冲突。

    PROTOCOL FOR CONFLICTING MEMORY TRANSACTIONS
    2.
    发明申请
    PROTOCOL FOR CONFLICTING MEMORY TRANSACTIONS 有权
    冲突内存交易协议

    公开(公告)号:US20140359230A1

    公开(公告)日:2014-12-04

    申请号:US13997900

    申请日:2011-12-20

    IPC分类号: G06F12/08

    摘要: Embodiments of the invention describe a cache coherency protocol that eliminates the need for ordering between message classes and also eliminates home tracker preallocation. Embodiments of the invention describe a less complex conflict detection and resolution mechanism (at the home agent) without any performance degradation in form of bandwidth or latency compared to prior art solutions.Embodiments of the invention describe a home agent that may receive request messages, e.g., data ownership request messages and data request messages, which include issuance data indicating an order of the respective message issued. Said home agent may determine whether an early or late conflict exists based, at least in part, on a received conflict response message and the issuance data of a most recent completed transaction.

    摘要翻译: 本发明的实施例描述了高速缓存一致性协议,其消除了在消息类之间排序的需要,并且还消除了家庭跟踪器预分配。 与现有技术的解决方案相比,本发明的实施例描述了一种不太复杂的冲突检测和解决机制(在归属代理),与带宽或延迟形式没有任何性能下降。 本发明的实施例描述了可以接收诸如数据所有权请求消息和数据请求消息的请求消息的归属代理,其包括指示所发出的各个消息的顺序的发布数据。 所述归属代理可以至少部分地基于接收到的冲突响应消息和最近完成的交易的发行数据来确定是否存在早期或晚期冲突。

    Providing A Directory Cache For Peripheral Devices
    5.
    发明申请
    Providing A Directory Cache For Peripheral Devices 失效
    为外围设备提供目录缓存

    公开(公告)号:US20120131282A1

    公开(公告)日:2012-05-24

    申请号:US12953120

    申请日:2010-11-23

    IPC分类号: G06F12/00

    CPC分类号: G06F12/0817

    摘要: In one embodiment, the present invention includes a processor having at least one core and uncore logic. The uncore logic can include a home agent to act as a guard to control access to a memory region. Either in the home agent or another portion of the uncore logic, a directory cache may be provided to store ownership information for a portion of the memory region owned by an agent coupled to the processor. In this way, when an access request for the memory region misses in the directory cache, a memory transaction can be avoided. Other embodiments are described and claimed.

    摘要翻译: 在一个实施例中,本发明包括具有至少一个核和非逻辑逻辑的处理器。 非逻辑逻辑可以包括用作控制对存储器区域的访问的保护的归属代理。 在归属代理或非逻辑逻辑的另一部分中,可以提供目录高速缓存以存储由耦合到处理器的代理拥有的存储器区域的一部分的所有权信息。 以这种方式,当存储器区域的访问请求在目录高速缓存中丢失时,可以避免存储器事务。 描述和要求保护其他实施例。

    Providing a directory cache for peripheral devices
    6.
    发明授权
    Providing a directory cache for peripheral devices 失效
    为外围设备提供目录缓存

    公开(公告)号:US08489822B2

    公开(公告)日:2013-07-16

    申请号:US12953120

    申请日:2010-11-23

    IPC分类号: G06F13/00

    CPC分类号: G06F12/0817

    摘要: In one embodiment, the present invention includes a processor having at least one core and uncore logic. The uncore logic can include a home agent to act as a guard to control access to a memory region. Either in the home agent or another portion of the uncore logic, a directory cache may be provided to store ownership information for a portion of the memory region owned by an agent coupled to the processor. In this way, when an access request for the memory region misses in the directory cache, a memory transaction can be avoided. Other embodiments are described and claimed.

    摘要翻译: 在一个实施例中,本发明包括具有至少一个核和非逻辑逻辑的处理器。 非逻辑逻辑可以包括用作控制对存储器区域的访问的保护的归属代理。 在归属代理或非逻辑逻辑的另一部分中,可以提供目录高速缓存以存储由耦合到处理器的代理拥有的存储器区域的一部分的所有权信息。 以这种方式,当存储器区域的访问请求在目录高速缓存中丢失时,可以避免存储器事务。 描述和要求保护其他实施例。

    Directory cache supporting non-atomic input/output operations
    7.
    发明授权
    Directory cache supporting non-atomic input/output operations 有权
    支持非原子输入/输出操作的目录缓存

    公开(公告)号:US09170946B2

    公开(公告)日:2015-10-27

    申请号:US13724214

    申请日:2012-12-21

    IPC分类号: G06F12/08

    摘要: Responsive to receiving a write request for a cache line from an input/output device, a caching agent of a first processor determines that the cache line is managed by a home agent of a second processor. The caching agent sends an ownership request for the cache line to the second processor. A home agent of the second processor receives the ownership request, generates an entry in a directory cache for the cache line, the entry identifying the remote caching agent as having ownership of the cache line, and grants ownership of the cache line to the remote caching agent. Responsive to receiving the grant of ownership for the cache line from the home agent an input/output controller of the first processor adds an entry for the cache line to an input/output write cache, the entry comprising a first indicator that the cache line is managed by the home agent of the second processor.

    摘要翻译: 响应于从输入/输出设备接收对高速缓存线的写入请求,第一处理器的高速缓存代理器确定高速缓存行由第二处理器的归属代理管理。 缓存代理向第二处理器发送高速缓存行的所有权请求。 第二处理器的归属代理接收所有权请求,在高速缓存行的目录高速缓存中生成条目,将远程高速缓存代理标识为具有高速缓存行的所有权的条目,并将高速缓存行的所有权授予远程缓存 代理商 响应于从所述归属代理接收对所述高速缓存行的所有权的许可,所述第一处理器的输入/输出控制器将用于所述高速缓存行的条目添加到输入/输出写入高速缓存,所述条目包括所述高速缓存行是 由第二处理器的归属代理管理。

    DIRECTORY CACHE SUPPORTING NON-ATOMIC INPUT/OUTPUT OPERATIONS
    8.
    发明申请
    DIRECTORY CACHE SUPPORTING NON-ATOMIC INPUT/OUTPUT OPERATIONS 有权
    目录缓存支持非原始输入/输出操作

    公开(公告)号:US20140181394A1

    公开(公告)日:2014-06-26

    申请号:US13724214

    申请日:2012-12-21

    IPC分类号: G06F12/08

    摘要: Responsive to receiving a write request for a cache line from an input/output device, a caching agent of a first processor determines that the cache line is managed by a home agent of a second processor. The caching agent sends an ownership request for the cache line to the second processor. A home agent of the second processor receives the ownership request, generates an entry in a directory cache for the cache line, the entry identifying the remote caching agent as having ownership of the cache line, and grants ownership of the cache line to the remote caching agent. Responsive to receiving the grant of ownership for the cache line from the home agent an input/output controller of the first processor adds an entry for the cache line to an input/output write cache, the entry comprising a first indicator that the cache line is managed by the home agent of the second processor.

    摘要翻译: 响应于从输入/输出设备接收对高速缓存线的写入请求,第一处理器的高速缓存代理器确定高速缓存行由第二处理器的归属代理管理。 缓存代理向第二处理器发送高速缓存行的所有权请求。 第二处理器的归属代理接收所有权请求,在高速缓存行的目录高速缓存中生成条目,将远程高速缓存代理标识为具有高速缓存行的所有权的条目,并将高速缓存行的所有权授予远程缓存 代理商 响应于从所述归属代理接收对所述高速缓存行的所有权的许可,所述第一处理器的输入/输出控制器将用于所述高速缓存行的条目添加到输入/输出写入高速缓存,所述条目包括所述高速缓存行是 由第二处理器的归属代理管理。