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公开(公告)号：US20140208141A1
公开(公告)日：2014-07-24
申请号：US13997386
申请日：2012-03-13
Applicant: Malini K. Bhandaru , Ankush Varma , James R. Vash , Monica Wong-Chan , Eric J. Dehaemer , Christopher Allan Poirier, SR. , Scott P. Bobholz
Inventor： Malini K. Bhandaru , Ankush Varma , James R. Vash , Monica Wong-Chan , Eric J. Dehaemer , Christopher Allan Poirier, SR. , Scott P. Bobholz
CPC classification number: G06F1/3243 , G06F1/3206 , G06F1/324 , G06F1/3296 , G06F9/3885 , G06F12/0802 , Y02D10/126 , Y02D10/172
Abstract: In one embodiment, the present invention includes a method for determining whether a number of stalled cores of a multicore processor is greater than a stall threshold. If so, a recommendation may be made that an operating frequency of system agent circuitry of the processor be increased. Then based on multiple recommendations, a candidate operating frequency of the system agent circuitry can be set. Other embodiments are described and claimed.
Abstract translation: 在一个实施例中，本发明包括一种用于确定多核处理器的多个停滞的核心是否大于失速阈值的方法。 如果是这样，可以建议增加处理器的系统代理电路的工作频率。 然后，基于多个建议，可以设置系统代理电路的候选工作频率。 描述和要求保护其他实施例。
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2.发明申请公开(公告)号：US20120079032A1
公开(公告)日：2012-03-29
申请号：US12889802
申请日：2010-09-24
Applicant: James R. Vash , Vida Vakilotojar , Bongjin Jung , Yen-Cheng Liu
Inventor： James R. Vash , Vida Vakilotojar , Bongjin Jung , Yen-Cheng Liu
CPC classification number: H04L67/10 , G06F15/17325
Abstract: Methods, apparatus and systems for facilitating one-way ordering of otherwise independent message classes. A one-way message ordering mechanism facilitates one-way ordering of messages of different message classes sent between interconnects employing independent pathways for the message classes. In one aspect, messages of a second message class may not pass messages of a first message class. Moreover, when messages of the first and second classes are received in sequence, the ordering mechanism ensures that messages of the first class are forwarded to, and received at, a next hop prior to forwarding messages of the second class.
Abstract translation: 用于促进独立消息类别的单向排序的方法，装置和系统。 单向消息排序机制有助于在使用消息类的独立路径的互连之间发送的不同消息类别的消息的单向排序。 在一个方面，第二消息类的消息可能不会传递第一消息类的消息。 此外，当顺序地接收到第一类和第二类的消息时，排序机制确保在转发第二类的消息之前将第一类的消息转发到下一跳并在其中接收。
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3.发明申请RETRY BASED PROTOCOL WITH SOURCE/RECEIVER FIFO RECOVERY AND ANTI-STARVATION MECHANISM TO SUPPORT DYNAMIC PIPELINE LENGTHENING FOR ECC ERROR CORRECTION 有权具有源/接收器FIFO恢复和反作用机制的重新构建协议支持动态管道加密用于ECC错误校正公开(公告)号：US20110161769A1
公开(公告)日：2011-06-30
申请号：US12978581
申请日：2010-12-26
Applicant: James R. Vash , Danielle N. Devereaux , Scott J. Erlanger , Robert E. Faber
Inventor： James R. Vash , Danielle N. Devereaux , Scott J. Erlanger , Robert E. Faber
CPC classification number: G06F11/10 , G06F11/1443 , H03M13/37 , H03M13/3723 , H03M13/6508 , H04L1/1874
Abstract: Methods and apparatus relating to retry based protocol with source/receiver FIFO (First-In, First-Out) buffer recovery and anti-starvation mechanism to support dynamic pipeline lengthening for ECC error correction are described. In an embodiment, upon detection of an error, a portion of transmitted data is stored in one or more storage devices before retransmission. Other embodiments are also described and claimed.
Abstract translation: 描述了基于重试协议的方法和设备，具有源/接收器FIFO（先进先出）缓冲器恢复和抗饥饿机制，以支持用于ECC纠错的动态管道延长。 在一个实施例中，一旦检测到错误，一部分传输的数据就被重新存储在一个或多个存储设备中。 还描述和要求保护其他实施例。
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公开(公告)号：US09323316B2
公开(公告)日：2016-04-26
申请号：US13997386
申请日：2012-03-13
Applicant: Malini K. Bhandaru , Ankush Varma , James R. Vash , Monica Wong-Chan , Eric J. Dehaemer , Christopher Allan Poirier, Sr. , Scott P. Bobholz
Inventor： Malini K. Bhandaru , Ankush Varma , James R. Vash , Monica Wong-Chan , Eric J. Dehaemer , Christopher Allan Poirier, Sr. , Scott P. Bobholz
CPC classification number: G06F1/3243 , G06F1/3206 , G06F1/324 , G06F1/3296 , G06F9/3885 , G06F12/0802 , Y02D10/126 , Y02D10/172
Abstract: In one embodiment, the present invention includes a method for determining whether a number of stalled cores of a multicore processor is greater than a stall threshold. If so, a recommendation may be made that an operating frequency of system agent circuitry of the processor be increased. Then based on multiple recommendations, a candidate operating frequency of the system agent circuitry can be set. Other embodiments are described and claimed.
Abstract translation: 在一个实施例中，本发明包括一种用于确定多核处理器的多个停滞的核心是否大于失速阈值的方法。 如果是这样，可以建议增加处理器的系统代理电路的工作频率。 然后，基于多个建议，可以设置系统代理电路的候选工作频率。 描述和要求保护其他实施例。
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公开(公告)号：US08769211B2
公开(公告)日：2014-07-01
申请号：US12644506
申请日：2009-12-22
Applicant: James R. Vash , Bongjin Jung , Rishan Tan
Inventor： James R. Vash , Bongjin Jung , Rishan Tan
CPC classification number: G06F12/0815 , G06F12/0842
Abstract: Systems, apparatus, and method of monitoring synchronization in a distributed cache are described. In an exemplary embodiment, a first and second processing core process a first and second thread respectively. A first and second distributed cache slices store data for either or both of the first and second processing cores. A first and second core interface co-located with the first and second processing cores respectively maintain a finite state machine (FSM) to be executed in response to receiving a request from a thread of its co-located processing core to monitor a cache line in the distributed cache.
Abstract translation: 描述了在分布式高速缓存中监视同步的系统，装置和方法。 在示例性实施例中，第一和第二处理核心分别处理第一和第二线程。 第一和第二分布式缓存片段存储用于第一和第二处理核心中的一个或两者的数据。 与第一和第二处理核心共同定位的第一和第二核心接口分别保持有待执行的有限状态机（FSM），以响应于从其同位处理核心的线程接收请求来监视高速缓存行 分布式缓存。
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Patent Agency Ranking
公开(公告)号：US20140181394A1
公开(公告)日：2014-06-26
申请号：US13724214
申请日：2012-12-21
Applicant: Herbert H. Hum , James R. Vash , Eric A. Gouldey , Ganesh Kumar , David Bubien , Manoj K. Arora , Luke Chang , Lavanya Nama , Mahak Gupta
Inventor： Herbert H. Hum , James R. Vash , Eric A. Gouldey , Ganesh Kumar , David Bubien , Manoj K. Arora , Luke Chang , Lavanya Nama , Mahak Gupta
IPC: G06F12/08
CPC classification number: G06F12/082 , G06F12/0824 , G06F12/0833 , G06F12/0835 , G06F2212/1016 , G06F2212/621
Abstract: Responsive to receiving a write request for a cache line from an input/output device, a caching agent of a first processor determines that the cache line is managed by a home agent of a second processor. The caching agent sends an ownership request for the cache line to the second processor. A home agent of the second processor receives the ownership request, generates an entry in a directory cache for the cache line, the entry identifying the remote caching agent as having ownership of the cache line, and grants ownership of the cache line to the remote caching agent. Responsive to receiving the grant of ownership for the cache line from the home agent an input/output controller of the first processor adds an entry for the cache line to an input/output write cache, the entry comprising a first indicator that the cache line is managed by the home agent of the second processor.
Abstract translation: 响应于从输入/输出设备接收对高速缓存线的写入请求，第一处理器的高速缓存代理器确定高速缓存行由第二处理器的归属代理管理。 缓存代理向第二处理器发送高速缓存行的所有权请求。 第二处理器的归属代理接收所有权请求，在高速缓存行的目录高速缓存中生成条目，将远程高速缓存代理标识为具有高速缓存行的所有权的条目，并将高速缓存行的所有权授予远程缓存 代理商 响应于从所述归属代理接收对所述高速缓存行的所有权的许可，所述第一处理器的输入/输出控制器将用于所述高速缓存行的条目添加到输入/输出写入高速缓存，所述条目包括所述高速缓存行是 由第二处理器的归属代理管理。
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7.发明授权Inter-queue anti-starvation mechanism with dynamic deadlock avoidance in a retry based pipeline 失效在基于重试的管道中具有动态死锁避免的队列间抗饥饿机制公开(公告)号：US08626968B2
公开(公告)日：2014-01-07
申请号：US12978586
申请日：2010-12-26
Applicant: James R. Vash , Bongjin Jung , Pritpal S. Ahuja
Inventor： James R. Vash , Bongjin Jung , Pritpal S. Ahuja
CPC classification number: G06F12/0815 , G06F13/1642 , G06F2212/621
Abstract: Methods and apparatus relating to an inter-queue anti-starvation mechanism with dynamic deadlock avoidance in a retry based pipeline are described. In one embodiment, logic may arbitrate between two queues based on various rules. The queues may store data including local or remote requests, data responses, non-data responses, external interrupts, etc. Other embodiments are also disclosed.
Abstract translation: 描述了在基于重试的管道中与具有动态死锁避免的队列间抗饥饿机制有关的方法和装置。 在一个实施例中，逻辑可以基于各种规则在两个队列之间仲裁。 队列可以存储包括本地或远程请求，数据响应，非数据响应，外部中断等的数据。还公开了其他实施例。
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8.发明授权Apparatus, system, and methods for facilitating one-way ordering of messages 有权用于促进消息的单向排序的装置，系统和方法公开(公告)号：US08554851B2
公开(公告)日：2013-10-08
申请号：US12889802
申请日：2010-09-24
Applicant: James R. Vash , Vida Vakilotojar , Bongjin Jung , Yen-Cheng Liu
Inventor： James R. Vash , Vida Vakilotojar , Bongjin Jung , Yen-Cheng Liu
IPC: G06F15/16
CPC classification number: H04L67/10 , G06F15/17325
Abstract: Methods, apparatus and systems for facilitating one-way ordering of otherwise independent message classes. A one-way message ordering mechanism facilitates one-way ordering of messages of different message classes sent between interconnects employing independent pathways for the message classes. In one aspect, messages of a second message class may not pass messages of a first message class. Moreover, when messages of the first and second classes are received in sequence, the ordering mechanism ensures that messages of the first class are forwarded to, and received at, a next hop prior to forwarding messages of the second class.
Abstract translation: 用于促进独立消息类别的单向排序的方法，装置和系统。 单向消息排序机制有助于在使用消息类的独立路径的互连之间发送的不同消息类别的消息的单向排序。 在一个方面，第二消息类的消息可能不会传递第一消息类的消息。 此外，当顺序地接收到第一类和第二类的消息时，排序机制确保在转发第二类的消息之前将第一类的消息转发到下一跳并在其中接收。
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公开(公告)号：US09170946B2
公开(公告)日：2015-10-27
申请号：US13724214
申请日：2012-12-21
Applicant: Herbert H. Hum , James R. Vash , Eric A. Gouldey , Ganesh Kumar , David Bubien , Manoj K. Arora , Luke Chang , Lavanya Nama , Mahak Gupta
Inventor： Herbert H. Hum , James R. Vash , Eric A. Gouldey , Ganesh Kumar , David Bubien , Manoj K. Arora , Luke Chang , Lavanya Nama , Mahak Gupta
IPC: G06F12/08
CPC classification number: G06F12/082 , G06F12/0824 , G06F12/0833 , G06F12/0835 , G06F2212/1016 , G06F2212/621
Abstract: Responsive to receiving a write request for a cache line from an input/output device, a caching agent of a first processor determines that the cache line is managed by a home agent of a second processor. The caching agent sends an ownership request for the cache line to the second processor. A home agent of the second processor receives the ownership request, generates an entry in a directory cache for the cache line, the entry identifying the remote caching agent as having ownership of the cache line, and grants ownership of the cache line to the remote caching agent. Responsive to receiving the grant of ownership for the cache line from the home agent an input/output controller of the first processor adds an entry for the cache line to an input/output write cache, the entry comprising a first indicator that the cache line is managed by the home agent of the second processor.
Abstract translation: 响应于从输入/输出设备接收对高速缓存线的写入请求，第一处理器的高速缓存代理器确定高速缓存行由第二处理器的归属代理管理。 缓存代理向第二处理器发送高速缓存行的所有权请求。 第二处理器的归属代理接收所有权请求，在高速缓存行的目录高速缓存中生成条目，将远程高速缓存代理标识为具有高速缓存行的所有权的条目，并将高速缓存行的所有权授予远程缓存 代理商 响应于从所述归属代理接收对所述高速缓存行的所有权的许可，所述第一处理器的输入/输出控制器将用于所述高速缓存行的条目添加到输入/输出写入高速缓存，所述条目包括所述高速缓存行是 由第二处理器的归属代理管理。
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10.发明申请公开(公告)号：US20140189239A1
公开(公告)日：2014-07-03
申请号：US13729579
申请日：2012-12-28
Applicant: Herbert H. Hum , Brinda Ganesh , James R. Vash , Ganesh Kumar , Leena K. Puthiyedath , Scott J. Erlanger , Eric J. Dehaemer , Adrian C. Moga , Michelle M. Sebot , Richard L. Carlson , David Bubien , Eric Delano
Inventor： Herbert H. Hum , Brinda Ganesh , James R. Vash , Ganesh Kumar , Leena K. Puthiyedath , Scott J. Erlanger , Eric J. Dehaemer , Adrian C. Moga , Michelle M. Sebot , Richard L. Carlson , David Bubien , Eric Delano
IPC: G06F12/08
CPC classification number: G06F12/0831 , G06F12/0811 , G06F12/084
Abstract: A processor of an aspect includes a plurality of logical processors each having one or more corresponding lower level caches. A shared higher level cache is shared by the plurality of logical processors. The shared higher level cache includes a distributed cache slice for each of the logical processors. The processor includes logic to direct an access that misses in one or more lower level caches of a corresponding logical processor to a subset of the distributed cache slices in a virtual cluster that corresponds to the logical processor. Other processors, methods, and systems are also disclosed.
Abstract translation: 一方面的处理器包括多个逻辑处理器，每个逻辑处理器具有一个或多个相应的较低级别的高速缓存。 共享的较高级缓存由多个逻辑处理器共享。 共享的较高级缓存包括用于每个逻辑处理器的分布式缓存片。 处理器包括用于将对应逻辑处理器的一个或多个较低级别高速缓存中的访问指向与对应于逻辑处理器的虚拟集群中的分布式高速缓存片段的子集的逻辑。 还公开了其他处理器，方法和系统。
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