公开(公告)号：US08479069B2

公开(公告)日：2013-07-02

申请号：US12728194

申请日：2010-03-19

申请人： Marc Miller ,  Steven Teig ,  Brad Hutchings ,  Danny Thom

发明人： Marc Miller ,  Steven Teig ,  Brad Hutchings ,  Danny Thom

IPC分类号： G01R31/28

CPC分类号： G01R31/3177 ,  G06F11/221 ,  G11C2029/0409

摘要： Some embodiments provide an integrated circuit (“IC”) with a primary circuit structure. The primary circuit structure is for performing multiple operations that implement a user design. The primary circuit structure includes multiple circuits. The IC also includes a secondary monitoring structure for monitoring multiple operations. The secondary monitoring structure includes a network communicatively coupled to multiple circuits of the primary circuit structure. The secondary monitoring circuit structure is for analyzing the monitored operations and reporting on the analysis to a circuit outside of the IC.

摘要翻译： 一些实施例提供具有主电路结构的集成电路（“IC”）。 主电路结构用于执行实现用户设计的多个操作。 主电路结构包括多个电路。 IC还包括用于监视多个操作的二级监视结构。 辅助监视结构包括通信地耦合到主电路结构的多个电路的网络。 二次监视电路结构用于分析被监控的操作并将分析报告给IC外的电路。

公开(公告)号：US20110060546A1

公开(公告)日：2011-03-10

申请号：US12728194

申请日：2010-03-19

申请人： Marc Miller ,  Steven Teig ,  Brad Hutchings ,  Danny Thom

发明人： Marc Miller ,  Steven Teig ,  Brad Hutchings ,  Danny Thom

IPC分类号： G01R27/28

CPC分类号： G01R31/3177 ,  G06F11/221 ,  G11C2029/0409

摘要： Some embodiments provide an integrated circuit (“IC”) with a primary circuit structure. The primary circuit structure is for performing multiple operations that implement a user design. The primary circuit structure includes multiple circuits. The IC also includes a secondary monitoring structure for monitoring multiple operations. The secondary monitoring structure includes a network communicatively coupled to multiple circuits of the primary circuit structure. The secondary monitoring circuit structure is for analyzing the monitored operations and reporting on the analysis to a circuit outside of the IC.

摘要翻译： 一些实施例提供具有主电路结构的集成电路（“IC”）。 主电路结构用于执行实现用户设计的多个操作。 主电路结构包括多个电路。 IC还包括用于监视多个操作的二级监视结构。 辅助监视结构包括通信地耦合到主电路结构的多个电路的网络。 二次监视电路结构用于分析被监控的操作并将分析报告给IC外的电路。

公开(公告)号：US20110029830A1

公开(公告)日：2011-02-03

申请号：US12679305

申请日：2008-09-19

申请人： Marc Miller ,  Steven Teig ,  Jason Redgrave ,  Brad Hutchings ,  Danny Thom

发明人： Marc Miller ,  Steven Teig ,  Jason Redgrave ,  Brad Hutchings ,  Danny Thom

IPC分类号： G06F11/07

CPC分类号： G01R31/3177 ,  G06F11/221 ,  G11C2029/0409

摘要： Some embodiments provide an integrated circuit (“IC”) with a primary circuit structure. The primary circuit structure is for performing multiple operations that implement a user design. The primary circuit structure includes multiple circuits. The IC also includes a secondary monitoring structure for monitoring multiple operations. The secondary monitoring structure includes a network communicatively coupled to multiple circuits of the primary circuit structure. The secondary monitoring circuit structure is for analyzing the monitored operations and reporting on the analysis to a circuit outside of the IC.

摘要翻译： 一些实施例提供具有主电路结构的集成电路（“IC”）。 主电路结构用于执行实现用户设计的多个操作。 主电路结构包括多个电路。 IC还包括用于监视多个操作的二级监视结构。 辅助监视结构包括通信地耦合到主电路结构的多个电路的网络。 二次监视电路结构用于分析被监控的操作并将分析报告给IC外的电路。

公开(公告)号：US06879590B2

公开(公告)日：2005-04-12

申请号：US10202108

申请日：2002-07-24

申请人： Soren Bo Pedersen ,  Radimir Shilshtut ,  Danny Thom ,  Sina Soltani ,  Lauren Trevor May

发明人： Soren Bo Pedersen ,  Radimir Shilshtut ,  Danny Thom ,  Sina Soltani ,  Lauren Trevor May

IPC分类号： H04L12/56 ,  H04M11/06 ,  H04L12/28

CPC分类号： H04L45/00 ,  H04L45/245 ,  H04M11/062 ,  Y02D50/30

摘要： Methods, apparatuses and systems facilitating the aggregation or bonding of physical communications links into higher-bandwidth logical links. A novel link bonding and encapsulation protocol scheme that optimizes the efficiency of data transfer across the physical links, while still allowing for desired Quality of Service (QoS) levels to high-priority traffic, such as voice data, with low delay requirements. Data streams are divided and concurrently transported over multiple physical links that are aggregated or bonded together to form one logical link. At the receive end, the original cell streams are recovered from the bonded logical links. In one embodiment, the physical links are xDSL links transmitting and receiving signals via conventional copper twisted-pair cabling. In one embodiment, the present invention allows telecommunications service providers to leverage their investments in existing twisted pair connection technologies to deliver high-bandwidth services to customers in a fast and cost-efficient manner.

摘要翻译： 便于将物理通信链路聚集或绑定到更高带宽逻辑链路中的方法，设备和系统。 一种新颖的链路绑定和封装协议方案，其优化跨物理链路的数据传输的效率，同时仍然允许具有低延迟要求的高优先级流量（例如语音数据）的期望的服务质量（QoS）水平。 数据流被划分并且通过多个物理链路并行传输，这些物理链路被聚合或结合在一起以形成一个逻辑链路。 在接收端，从绑定的逻辑链路恢复原始信元流。 在一个实施例中，物理链路是通过常规铜双绞线电缆发送和接收信号的xDSL链路。 在一个实施例中，本发明允许电信服务提供商利用他们对现有双绞线连接技术的投资，以快速且具有成本效益的方式向客户提供高带宽服务。

公开(公告)号：US06760327B1

公开(公告)日：2004-07-06

申请号：US09452829

申请日：1999-12-01

申请人： Earl B. Manchester ,  Barry W. Field ,  Kenneth M. Buckland ,  Charles R. Dyer ,  Riccardo G. Dorbolo ,  Danny Thom ,  Jan C. Hobbel ,  Soren B. Pedersen ,  Thomas A. Potter

发明人： Earl B. Manchester ,  Barry W. Field ,  Kenneth M. Buckland ,  Charles R. Dyer ,  Riccardo G. Dorbolo ,  Danny Thom ,  Jan C. Hobbel ,  Soren B. Pedersen ,  Thomas A. Potter

IPC分类号： H04L1228

CPC分类号： H04L49/606 ,  H04L12/6402

摘要： A rate adjustable backplane includes a set of switch slots configured to receive one or more switch cards forming a switch core and a plurality of line slots each configured to receive a line card. A low speed bus couples the line slots to the set of switch slots. A high speed bus also couples the line slots to the set of switch slots. Each line slot includes a low speed connector coupled to the low speed bus and a high speed connector coupled to the high speed bus. The low speed connector is adapted to receive a mating connector of a line card to establish a low speed communication connection between the line card and the switch core. The high speed connector is adapted to receive a mating connector of the line card to establish a high speed link between the line card and the switch core.

摘要翻译： 速率可调背板包括一组开关槽，其被配置为接收形成开关芯的一个或多个开关卡和多个配置成接收线卡的线槽。 低速总线将线路插槽连接到交换机插槽组。 高速总线也将线槽耦合到一组开关插槽。 每个线槽包括耦合到低速总线的低速连接器和耦合到高速总线的高速连接器。 低速连接器适于接收线路卡的匹配连接器，以在线路卡和交换机核心之间建立低速通信连接。 高速连接器适于接收线路卡的匹配连接器，以在线路卡和交换机核心之间建立高速链路。

公开(公告)号：US07006500B1

公开(公告)日：2006-02-28

申请号：US10334051

申请日：2002-12-30

申请人： Soren Bo Pedersen ,  Radimir Shilshtut ,  Danny Thom ,  Sina Soltani ,  Manish Lohani

发明人： Soren Bo Pedersen ,  Radimir Shilshtut ,  Danny Thom ,  Sina Soltani ,  Manish Lohani

IPC分类号： H04L12/28 ,  H04L12/56

CPC分类号： H04L45/00 ,  H04L45/245 ,  H04M11/062 ,  Y02D50/30

摘要： Methods, apparatuses and systems facilitating the aggregation or bonding of communications paths into a higher-bandwidth, logical communications path. Embodiments of the present invention can be applied to bond different physical links (e.g., xDSL over twisted pairs), different channels on the same physical line, or even different channels or frequencies in a wireless communications network. The present invention further provides methods, apparatuses and systems facilitating the re-sequencing of data flows transmitted across bonded communications paths. In one embodiment, the re-sequencing methodology of the present invention adapts to the transmission delays (both absolute and relative) across the bonded communications path.

摘要翻译： 促进将通信路径聚合或结合到更高带宽的逻辑通信路径中的方法，装置和系统。 本发明的实施例可以应用于在无线通信网络中绑定不同的物理链路（例如，双绞线上的xDSL），相同物理线路上的不同信道，或甚至不同的信道或频率。 本发明进一步提供了便于对通过绑定通信路径传输的数据流进行重排序的方法，装置和系统。 在一个实施例中，本发明的重排序方法适应跨越绑定通信路径的传输延迟（绝对和相对）。

公开(公告)号：US06621828B1

公开(公告)日：2003-09-16

申请号：US09452759

申请日：1999-12-01

申请人： Barry W. Field ,  Kenneth M. Buckland ,  Charles R. Dyer ,  Riccardo G. Dorbolo ,  Danny Thom ,  Jan C. Hobbel ,  Soren B. Pedersen ,  Thomas A. Potter

发明人： Barry W. Field ,  Kenneth M. Buckland ,  Charles R. Dyer ,  Riccardo G. Dorbolo ,  Danny Thom ,  Jan C. Hobbel ,  Soren B. Pedersen ,  Thomas A. Potter

IPC分类号： H04J316

CPC分类号： H04Q11/04 ,  H04Q2213/13103 ,  H04Q2213/1329 ,  H04Q2213/13292 ,  H04Q2213/13299 ,  H04Q2213/13361 ,  H04Q2213/13362 ,  H04Q2213/13393

摘要： A switch card for telecommunications node includes a shared memory operable to store traffic channels. A time slot interchanger (TSI) is coupled to a first bus and to the shared memory. The TSI is operable based on predefined switching instructions to access the shared memory to stored traffic channels received from the first bus and to retrieve traffic channels for transmission on the first bus. An asynchronous transfer mode (ATM) switch is operable to switch a traffic cell based on header information in the traffic cell. A traffic converter is operable to convert traffic channels retrieved from the shared memory to traffic cells for processing by a bus fuser and to convert traffic cells to traffic channels for storage in the shared memory. The bus fuser is coupled to the shared memory through the traffic converter, the ATM switch, and a second bus. The bus fuser is operable to receive a traffic cell from each one of the traffic converter, the ATM switch, and the second bus and to route the traffic cell to another one of the traffic converter, the ATM switch, and the second bus.

摘要翻译： 用于电信节点的交换卡包括可操作以存储业务信道的共享存储器。 时隙交换器（TSI）耦合到第一总线和共享存储器。 TSI可以基于预定义的切换指令来操作，以将共享存储器存储到从第一总线接收的存储的业务信道，并且检索用于在第一总线上传输的业务信道。 异步传输模式（ATM）交换机可操作以基于业务信元中的报头信息来切换业务信元。 业务转换器可操作以将从共享存储器检索的业务信道转换成业务信元以供总线定影器处理，并将业务信元转换为业务信道以存储在共享存储器中。 总线定影器通过流量转换器，ATM交换机和第二总线耦合到共享存储器。 总线定影器可操作以从业务转换器，ATM交换机和第二总线中的每一个接收业务信元，并将业务小区路由到业务转换器，ATM交换机和第二总线中的另一个。