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1.发明申请PHASE LOCKED LOOP AND METHOD FOR ADJUSTING THE FREQUENCY AND PHASE IN THE PHASE LOCKED LOOP 有权相位锁定环路和相位锁定环路中的频率和相位调整方法公开(公告)号：US20070075785A1
公开(公告)日：2007-04-05
申请号：US11469423
申请日：2006-08-31
申请人： Marcel Kossel , Thomas Morf , Martin Schmatz , Silvan Wehrli
发明人： Marcel Kossel , Thomas Morf , Martin Schmatz , Silvan Wehrli
IPC分类号： H03L7/00
摘要： A phase locked loop (PLL) which includes a phase frequency detector coupled with a time to digital converter capable of comparing a reference signal with an oscillator signal and generating a digital value representing the phase difference between the reference signal and the oscillator signal. The PLL further includes a state machine for phase acquisition that is capable of generating a control value depending on the digital value, and a controllable oscillator that is capable of generating the oscillator signal depending on the control value.
摘要翻译： 一种锁相环（PLL），其包括与时间数字转换器耦合的相位频率检测器，其能够将参考信号与振荡器信号进行比较，并产生表示参考信号和振荡器信号之间的相位差的数字值。 PLL还包括能够根据数字值产生控制值的相位获取状态机，以及能够根据控制值产生振荡器信号的可控振荡器。
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2.发明授权公开(公告)号：US07403073B2
公开(公告)日：2008-07-22
申请号：US11469423
申请日：2006-08-31
IPC分类号： H03L7/00
摘要： A phase locked loop (PLL) which includes a phase frequency detector coupled with a time to digital converter capable of comparing a reference signal with an oscillator signal and generating a digital value representing the phase difference between the reference signal and the oscillator signal. The PLL further includes a state machine for phase acquisition that is capable of generating a control value depending on the digital value, and a controllable oscillator that is capable of generating the oscillator signal depending on the control value.
摘要翻译： 一种锁相环（PLL），其包括与时间数字转换器耦合的相位频率检测器，其能够将参考信号与振荡器信号进行比较，并产生表示参考信号和振荡器信号之间的相位差的数字值。 PLL还包括能够根据数字值产生控制值的相位获取状态机，以及能够根据控制值产生振荡器信号的可控振荡器。
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3.发明授权公开(公告)号：US07839221B2
公开(公告)日：2010-11-23
申请号：US12132960
申请日：2008-06-04
IPC分类号： H03L7/00
摘要： A phase locked loop (PLL) which includes a phase frequency detector coupled with a time to digital converter capable of comparing a reference signal with an oscillator signal and generating a digital value representing the phase difference between the reference signal and the oscillator signal. The PLL further includes a state machine for phase acquisition that is capable of generating a control value depending on the digital value, and a controllable oscillator that is capable of generating the oscillator signal depending on the control value.
摘要翻译： 一种锁相环（PLL），其包括与时间数字转换器耦合的相位频率检测器，其能够将参考信号与振荡器信号进行比较，并产生表示参考信号和振荡器信号之间的相位差的数字值。 PLL还包括能够根据数字值产生控制值的相位获取状态机，以及能够根据控制值产生振荡器信号的可控振荡器。
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4.发明申请PHASE LOCKED LOOP AND METHOD FOR ADJUSTING THE FREQUENCY AND PHASE IN THE PHASE LOCKED LOOP 有权相位锁定环路和相位锁定环路中的频率和相位调整方法公开(公告)号：US20080246522A1
公开(公告)日：2008-10-09
申请号：US12132960
申请日：2008-06-04
IPC分类号： H03L7/08
摘要： A phase locked loop (PLL) which includes a phase frequency detector coupled with a time to digital converter capable of comparing a reference signal with an oscillator signal and generating a digital value representing the phase difference between the reference signal and the oscillator signal. The PLL further includes a state machine for phase acquisition that is capable of generating a control value depending on the digital value, and a controllable oscillator that is capable of generating the oscillator signal depending on the control value.
摘要翻译： 一种锁相环（PLL），其包括与时间数字转换器耦合的相位频率检测器，其能够将参考信号与振荡器信号进行比较，并产生表示参考信号和振荡器信号之间的相位差的数字值。 PLL还包括能够根据数字值产生控制值的相位获取状态机，以及能够根据控制值产生振荡器信号的可控振荡器。
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