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    Instruction memory system for multi-processor environment and disjoint tasks
    1.
    发明授权
    Instruction memory system for multi-processor environment and disjoint tasks 有权
    指令存储系统，用于多处理器环境和不相交任务

    公开(公告)号：US06760743B1

    公开(公告)日：2004-07-06

    申请号：US09477757

    申请日：2000-01-04

    申请人： Marco C. Heddes ,  Mark Anthony Rinaldi ,  Brian Alan Youngman

    发明人： Marco C. Heddes ,  Mark Anthony Rinaldi ,  Brian Alan Youngman

    IPC分类号： G06F900

    CPC分类号： G06F9/3802 ,  G06F9/3851

    摘要： An instruction memory system is shared by a plurality of processors and the system utilizes an increased bandwidth to support the combined number of processors. The total instruction address space is divided into code segments according to the disjoint tasks to be performed. The instruction codes of each processor are consolidated into one copy for control instructions and duplicate copies for other disjoint tasks such as inbound requests and outbound requests that have greater processor contention. Interleaving of the memory arrays for certain disjoint tasks serves to provide a larger number of instructions for these tasks. The system utilizes arbiters to receive all disjoint tasks and to control multiplexors that send addresses to memory arrays.

    摘要翻译： 指令存储器系统由多个处理器共享，并且系统利用增加的带宽来支持组合的处理器数量。 总指令地址空间根据要执行的不相交任务分为代码段。 每个处理器的指令代码被合并到一个副本中，用于控制指令和其他不相交任务的重复副本，例如具有更大处理器争用的入站请求和出站请求。 用于某些不相交任务的存储器阵列的交织用于为这些任务提供更多数量的指令。 该系统利用仲裁器接收所有不相交的任务，并控制向存储器阵列发送地址的多路复用器。

    Software management tree implementation for a network processor
    6.
    发明授权
    Software management tree implementation for a network processor 失效
    网络处理器的软件管理树实现

    公开(公告)号：US07107265B1

    公开(公告)日：2006-09-12

    申请号：US09545100

    申请日：2000-04-06

    申请人： Jean Louis Calvignac ,  Marco C. Heddes ,  Clark Debs Jeffries ,  Piyush Chunilal Patel ,  Mark Anthony Rinaldi

    发明人： Jean Louis Calvignac ,  Marco C. Heddes ,  Clark Debs Jeffries ,  Piyush Chunilal Patel ,  Mark Anthony Rinaldi

    IPC分类号： G06F17/30 ,  G06F15/00 ,  G06F9/44

    CPC分类号： H04L45/742 ,  G06F17/30961 ,  G06F17/30985 ,  Y10S707/99933 ,  Y10S707/99936 ,  Y10S707/99937

    摘要： Novel data structures, methods and apparatus for a Software Managed Tree (SMT) which provides a mechanism to create tree structures that follow a search mechanism defined by a control point processor. The search mechanism does not require storage on the previous pointer and uses only a forward pointer along with a next bit or group of bits to test thereby reducing storage space for nodes. The search mechanism processes multiple filter rules for an application without requiring multiple searches and also allows various filter rules to be chained. Two patterns of the same length are stored in each leaf to define a range compare. A compare at the end operation is either a compare under range or a compare under mask. In a compare under range, the input key is checked to determine if it is in the range defined by the two patterns. In a compare under mask, the bits in the input key are compared with the bits in a first leaf pattern under a mask specified in a second leaf pattern.

    摘要翻译： 用于软件管理树（SMT）的新型数据结构，方法和装置，其提供了一种机制，用于创建遵循由控制点处理器定义的搜索机制的树结构。 搜索机制不需要在前一个指针上存储，并且仅使用前向指针以及下一个位或一组位来进行测试，从而减少节点的存储空间。 搜索机制处理应用程序的多个过滤器规则，而不需要多次搜索，并且还允许链接各种过滤器规则。 在每个叶中存储相同长度的两个图案以定义范围比较。 在最终操作中的比较是在范围之下的比较或掩码下的比较。 在范围比较范围内，检查输入键以确定是否在两种模式定义的范围内。 在掩码下的比较中，将输入密钥中的比特与在第二叶图案中指定的掩码下的第一叶图案中的比特进行比较。

    Network processor/software control architecture
    7.
    发明授权
    Network processor/software control architecture 失效
    网络处理器/软件控制架构

    公开(公告)号：US06898179B1

    公开(公告)日：2005-05-24

    申请号：US09544896

    申请日：2000-04-07

    申请人： Brian Mitchell Bass ,  Jean Louis Calvignac ,  Anthony Matteo Gallo ,  Marco C. Heddes ,  Mark Anthony Rinaldi ,  Michael Steven Siegel ,  Colin Beaton Verrilli ,  Fabrice Jean Verplanken

    发明人： Brian Mitchell Bass ,  Jean Louis Calvignac ,  Anthony Matteo Gallo ,  Marco C. Heddes ,  Mark Anthony Rinaldi ,  Michael Steven Siegel ,  Colin Beaton Verrilli ,  Fabrice Jean Verplanken

    IPC分类号： G06F11/00 ,  H04B7/216 ,  H04L1/16 ,  H04L12/26

    CPC分类号： G06F15/17

    摘要： The transport protocol for communicating between general purpose processors acting as contact points and network processors in a packet processing environment such as Ethernet is provided. In such an environment, there is at least one single control point processor (CP) and a plurality of network processors (NP), sometimes referred to as blades. A typical system could contain two to sixteen network processors, and each network processor connects to a plurality of devices which communicate with each other over a network transport, such as Ethernet. The CP typically controls the functionality and the functioning of the network processors to function in a way that connects one end user with another, whether or not the end user is on the same network processor or a different network processor. There are three types of communication provided; first, there is communication generally referred to as control services and normally there will be only one pico processor which operates as a GCH (guided cell handler) and only one that operates as a guided tree handler (GTH). A path is provided for the controls to the GCH and the GTH commands, and a separate path is provided for the data frames between the GDH's (general data handler) and the CP.

    摘要翻译： 提供了用于在诸如以太网的分组处理环境中用作接触点的通用处理器和网络处理器之间进行通信的传输协议。 在这样的环境中，存在至少一个单个控制点处理器（CP）和多个网络处理器（NP），有时称为刀片。 典型的系统可以包含两到十六个网络处理器，并且每个网络处理器连接到通过诸如以太网的网络传输彼此通信的多个设备。 CP通常控制网络处理器的功能和功能，以使终端用户与另一终端用户相连的方式起作用，无论终端用户是否在同一个网络处理器或不同的网络处理器上。 提供三种通讯方式; 首先，通常被称为控制服务的通信，并且通常将只有一个微微处理器作为GCH（引导的单元处理器）操作，并且只有一个作为引导树处理器（GTH）操作。 为GCH和GTH命令的控制提供路径，并为GDH（通用数据处理程序）和CP之间的数据帧提供单独的路径。

    Multiple logical interfaces to a shared coprocessor resource
    9.
    发明授权
    Multiple logical interfaces to a shared coprocessor resource 失效
    到共享协处理器资源的多个逻辑接口

    公开(公告)号：US06829697B1

    公开(公告)日：2004-12-07

    申请号：US09656582

    申请日：2000-09-06

    申请人： Gordon Taylor Davis ,  Marco C. Heddes ,  Ross Boyd Leavens ,  Mark Anthony Rinaldi

    发明人： Gordon Taylor Davis ,  Marco C. Heddes ,  Ross Boyd Leavens ,  Mark Anthony Rinaldi

    IPC分类号： G06F1500

    CPC分类号： G06F15/7864

    摘要： An embedded processor complex contains multiple protocol processor units (PPUs). Each unit includes at least one, and preferably two independently functioning core language processors (CLPs). Each CLP supports dual threads thread which interact through logical coprocessor execution or data interfaces with a plurality of special purpose coprocessors that serve each PPU. Operating instructions enable the PPU to identify long and short latency events and to control and shift priority for thread execution based on this identification. The instructions also enable the conditional execution of specific coprocessor operations upon the occurrence or non occurrence of certain specified events.

    摘要翻译： 嵌入式处理器复合体包含多个协议处理器单元（PPU）。 每个单元包括至少一个，优选两个独立运行的核心语言处理器（CLP）。 每个CLP支持双线程线程，其通过逻辑协处理器执行或数据接口与多个为每个PPU服务的专用协处理器进行交互。 操作指令使PPU能够识别长时间和短的延迟事件，并根据此标识控制和转移线程执行的优先级。 指令还可以在某些指定事件的发生或不发生时使特定协处理器操作的条件执行。

    Apparatus and method to access computer memory by processing object data as sub-object and shape parameter
    10.
    发明授权
    Apparatus and method to access computer memory by processing object data as sub-object and shape parameter 失效

    公开(公告)号：US06463500B1

    公开(公告)日：2002-10-08

    申请号：US09477775

    申请日：2000-01-04

    申请人： Marco C. Heddes ,  Piyush Chunilal Patel ,  Mark Anthony Rinaldi

    发明人： Marco C. Heddes ,  Piyush Chunilal Patel ,  Mark Anthony Rinaldi

    IPC分类号： G06F1200

    CPC分类号： G06F17/30607 ,  G06F12/0207 ,  G06F17/3061

    摘要： A method is provided for utilizing a memory system which allows for the fast and efficient writing and reading of objects to and from diverse memory chips. A computer system and memory system complex according to method is also provided. The invention defines objects in terms of “shapes.” The shape of an object is defined by two parameters: “Width” and “Height.” Memory system memory chips may comprise sets of different kinds of memory modules which vary in terms of access speed, latency and memory width, such as for example DRAM or SRAM memory modules. The Height of an object denotes the number of consecutive address locations at which the object is stored on a memory module. The Width of an object denotes the number of memory modules at which the object is stored. An advantage of the invention is that objects are defined in terms of “sub-objects” optimized for the memory system memory modules. The sub-objects match the line-width of the memory, thereby allowing the objects to be efficiently written to different memories or memory banks. A further advantage of the invention is that the sub-object shape is transparent to the requester (i.e. transparent to application assembly language). A further advantage of the invention is that sub-objects are handled independently by the memory arbiter, i.e. they can be written to the memory or read from the memory in any order. The complex may further comprise a Tree Search Memory (TSM) system that utilizes a “tree” object hierarchy to perform high-speed memory lookups. Shaping is used to specify how an object is stored in the TSM. The trees consist of different kinds of objects with different shapes. An important advantage of the invention is that the concept of shapes can be used for memory bandwidth distribution and performance increase, allowing objects that are frequently read from memory to be distributed in specific sub-object ordering.