公开(公告)号：US20060110892A1

公开(公告)日：2006-05-25

申请号：US10996319

申请日：2004-11-22

申请人： Marius Orlowski ,  Mark Foisy ,  Olubunmi Adetutu

发明人： Marius Orlowski ,  Mark Foisy ,  Olubunmi Adetutu

IPC分类号： H01L21/76

CPC分类号： H01L29/7842 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/823807 ,  H01L21/823878

摘要： A semiconductor fabrication process includes patterning a hard mask over a semiconductor substrate to expose an isolation region and forming a trench in the isolation region. A flowable dielectric is deposited in the trench to partially fill the trench and a capping dielectric is deposited overlying the first oxide to fill the trench. The substrate may be a silicon on insulator (SOI) substrate including a buried oxide (BOX) layer and the trench may extend partially into the BOX layer. The flowable dielectric may be a spin deposited flowable oxide or a CVD BPSG oxide. The flowable dielectric isolation structure provides a buffer that prevents stress induced on one side of the isolation structure from creating stress on the other side of the structure. Thus, for example, compressive stress created by forming silicon germanium on silicon in PMOS regions does not create compressive stress in NMOS regions.

摘要翻译： 半导体制造工艺包括在半导体衬底上图案化硬掩模以暴露隔离区域并在隔离区域中形成沟槽。 在沟槽中沉积可流动电介质以部分地填充沟槽，并且覆盖覆盖第一氧化物的覆盖电介质以填充沟槽。 衬底可以是包括掩埋氧化物（BOX）层的绝缘体上硅（SOI）衬底，并且沟槽可以部分地延伸到BOX层中。 可流动电介质可以是自旋沉积的可流动氧化物或CVD BPSG氧化物。 可流动介电隔离结构提供了缓冲器，其防止在隔离结构的一侧上引起的应力在结构的另一侧上产生应力。 因此，例如，通过在PMOS区域中的硅上形成硅锗产生的压缩应力在NMOS区域中不产生压应力。

公开(公告)号：US20070166902A1

公开(公告)日：2007-07-19

申请号：US11331958

申请日：2006-01-13

申请人： Marius Orlowski ,  Olubunmi Adetutu ,  Philllip Stout

发明人： Marius Orlowski ,  Olubunmi Adetutu ,  Philllip Stout

IPC分类号： H01L21/8234 ,  H01L21/336

CPC分类号： H01L21/28114 ,  H01L29/42376 ,  H01L29/6659 ,  H01L29/7833

摘要： A semiconductor process and apparatus uses a predetermined sequence of patterning and etching steps to etch a gate stack (30, 32) formed over a substrate (36), thereby forming an etched gate (33) having a vertical sidewall profile (35). By constructing the gate stack (30, 32) with a graded material composition of silicon-based layers, the composition of which is selected to counteract the etching tendencies of the predetermined sequence of patterning and etching steps, a more idealized vertical gate sidewall profile (35) may be obtained.

摘要翻译： 半导体工艺和设备使用预定的图案化和蚀刻步骤序列来蚀刻在衬底（36）上形成的栅极堆叠（30,32），由此形成具有垂直侧壁轮廓（35）的蚀刻栅极（33）。 通过用硅基层的分级材料组成构造栅极堆叠（30,32），其组成被选择以抵消预定的图案化和蚀刻步骤的蚀刻趋势，更理想的垂直栅极侧壁轮廓（ 35）。

公开(公告)号：US20060084235A1

公开(公告)日：2006-04-20

申请号：US10965964

申请日：2004-10-15

申请人： Alexander Barr ,  Olubunmi Adetutu ,  Bich-Yen Nguyen ,  Marius Orlowski ,  Mariam Sadaka ,  Voon-Yew Thean ,  Ted White

发明人： Alexander Barr ,  Olubunmi Adetutu ,  Bich-Yen Nguyen ,  Marius Orlowski ,  Mariam Sadaka ,  Voon-Yew Thean ,  Ted White

IPC分类号： H01L21/336

CPC分类号： H01L29/66772 ,  H01L29/66636 ,  H01L29/78618

摘要： A semiconductor fabrication process includes forming a transistor gate overlying an SOI wafer having a semiconductor top layer over a buried oxide layer (BOX) over a semiconductor substrate. Source/drain trenches, disposed on either side of the gate, are etched into the BOX layer. Source/drain structures are formed within the trenches. A depth of the source/drain structures is greater than the thickness of the top silicon layer and an upper surface of the source/drain structures coincides approximately with the transistor channel whereby vertical overlap between the source/drain structures and the gate is negligible. The trenches preferably extend through the BOX layer to expose a portion of the silicon substrate. The source/drain structures are preferably formed epitaxially and possibly in two stages including an oxygen rich stage and an oxygen free stage. A thermally anneal between the two epitaxial stages will form an isolation dielectric between the source/drain structure and the substrate.

摘要翻译： 半导体制造工艺包括在半导体衬底上的掩埋氧化物层（BOX）上形成半导体顶层的SOI晶片的晶体管栅极。 设置在栅极两侧的源极/漏极沟槽被蚀刻到BOX层中。 源极/漏极结构形成在沟槽内。 源极/漏极结构的深度大于顶部硅层的厚度，并且源极/漏极结构的上表面大致与晶体管沟道重合，源极/漏极结构与栅极之间的垂直重叠可忽略不计。 沟槽优选地延伸穿过BOX层以暴露硅衬底的一部分。 源极/漏极结构优选外延地形成，并且可能包括富氧阶段和无氧阶段的两个阶段。 两个外延级之间的热退火将在源极/漏极结构和衬底之间形成隔离电介质。

公开(公告)号：US20050170604A1

公开(公告)日：2005-08-04

申请号：US10771855

申请日：2004-02-04

申请人： Marius Orlowski ,  Olubunmi Adetutu ,  Alexander Barr

发明人： Marius Orlowski ,  Olubunmi Adetutu ,  Alexander Barr

IPC分类号： H01L21/336 ,  H01L29/786 ,  H01L21/8234

CPC分类号： H01L29/66772 ,  H01L29/785 ,  H01L29/78603

摘要： A semiconductor on insulator transistor is formed beginning with a bulk silicon substrate. An active region is defined in the substrate and an oxygen-rich silicon layer that is monocrystalline is formed on a top surface of the active region. On this oxygen-rich silicon layer is grown an epitaxial layer of silicon. After formation of the epitaxial layer of silicon, the oxygen-rich silicon layer is converted to silicon oxide while at least a portion of the epitaxial layer of silicon remains as monocrystalline silicon. This is achieved by applying high temperature water vapor to the epitaxial layer. The result is a silicon on insulator structure useful for making a transistor in which the gate dielectric is on the remaining monocrystalline silicon, the gate is on the gate dielectric, and the channel is in the remaining monocrystalline silicon under the gate.

摘要翻译： 半导体绝缘体晶体管以体硅衬底开始形成。 在衬底中限定有源区，并且在有源区的顶表面上形成单晶的富氧硅层。 在该富氧硅层上生长硅的外延层。 在形成硅的外延层之后，将富氧硅层转化为氧化硅，而硅的外延层的至少一部分保留为单晶硅。 这通过将高温水蒸汽施加到外延层来实现。 结果是用于制造晶体管的绝缘体上硅结构，其中栅极电介质位于剩余的单晶硅上，栅极位于栅极电介质上，沟道位于栅极之下的剩余单晶硅中。

公开(公告)号：US20060194384A1

公开(公告)日：2006-08-31

申请号：US11382432

申请日：2006-05-09

申请人： Suresh Venkatesan ,  Mark Foisy ,  Michael Mendicino ,  Marius Orlowski

发明人： Suresh Venkatesan ,  Mark Foisy ,  Michael Mendicino ,  Marius Orlowski

IPC分类号： H01L21/8238

CPC分类号： H01L21/84 ,  H01L21/823807 ,  H01L27/1203

摘要： A semiconductor device structure uses two semiconductor layers to separately optimize N and P channel transistor carrier mobility. The conduction characteristic for determining this is a combination of material type of the semiconductor, crystal plane, orientation, and strain. Hole mobility is improved in P channel transistors when the conduction characteristic is characterized by the semiconductor material being silicon germanium, the strain being compressive, the crystal plane being (100), and the orientation being . In the alternative, the crystal plane can be (111) and the orientation in such case is unimportant. The preferred substrate for N-type conduction is different from the preferred (or optimum) substrate for P-type conduction. The N channel transistors preferably have tensile strain, silicon semiconductor material, and a (100) plane. With the separate semiconductor layers, both the N and P channel transistors can be optimized for carrier mobility.

摘要翻译： 半导体器件结构使用两个半导体层来分别优化N沟道晶体管和P沟道晶体管的迁移率。 用于确定的导电特性是半导体的材料类型，晶面，取向和应变的组合。 当导电特性的特征在于半导体材料为硅锗时，p型沟道晶体管的空穴迁移率得到改善，应变为压缩，晶面为（100），取向为100。 或者，晶面可以是（111），在这种情况下的取向是不重要的。 用于N型导电的优选衬底不同于用于P型导电的优选（或最佳）衬底。 N沟道晶体管优选具有拉伸应变，硅半导体材料和（100）平面。 通过分开的半导体层，N沟道晶体管和P沟道晶体管都可以优化载流子迁移率。

公开(公告)号：US20050275018A1

公开(公告)日：2005-12-15

申请号：US10865351

申请日：2004-06-10

申请人： Suresh Venkatesan ,  Mark Foisy ,  Michael Mendicino ,  Marius Orlowski

发明人： Suresh Venkatesan ,  Mark Foisy ,  Michael Mendicino ,  Marius Orlowski

IPC分类号： H01L21/8234 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12

CPC分类号： H01L21/84 ,  H01L21/823807 ,  H01L27/1203

摘要： A semiconductor device structure uses two semiconductor layers to separately optimize N and P channel transistor carrier mobility. The conduction characteristic for determining this is a combination of material type of the semiconductor, crystal plane, orientation, and strain. Hole mobility is improved in P channel transistors when the conduction characteristic is characterized by the semiconductor material being silicon germanium, the strain being compressive, the crystal plane being (100), and the orientation being . In the alternative, the crystal plane can be (111) and the orientation in such case is unimportant. The preferred substrate for N-type conduction is different from the preferred (or optimum) substrate for P-type conduction. The N channel transistors preferably have tensile strain, silicon semiconductor material, and a (100) plane. With the separate semiconductor layers, both the N and P channel transistors can be optimized for carrier mobility.

摘要翻译： 半导体器件结构使用两个半导体层来分别优化N沟道晶体管和P沟道晶体管的载流子迁移率。 用于确定的导电特性是半导体的材料类型，晶面，取向和应变的组合。 当导电特性的特征在于半导体材料为硅锗时，p型沟道晶体管的空穴迁移率得到改善，应变为压缩，晶面为（100），取向为100。 或者，晶面可以是（111），在这种情况下的取向是不重要的。 用于N型导电的优选衬底不同于用于P型导电的优选（或最佳）衬底。 N沟道晶体管优选具有拉伸应变，硅半导体材料和（100）平面。 通过分开的半导体层，N沟道晶体管和P沟道晶体管都可以优化载流子迁移率。

公开(公告)号：US20170155045A1

公开(公告)日：2017-06-01

申请号：US15365445

申请日：2016-11-30

申请人： Marius Orlowski ,  Gargi Ghosh ,  Anshuman Verma

发明人： Marius Orlowski ,  Gargi Ghosh ,  Anshuman Verma

IPC分类号： H01L45/00 ,  H01L27/24

CPC分类号： H01L45/149 ,  G11C11/5614 ,  G11C13/0011 ,  G11C2013/0078 ,  H01L27/2472 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/145 ,  H01L45/146

摘要： A memory device having a first array of first electrodes extending along a first direction made from a first material and a second array of second electrodes extending along a second direction made from a second material. An intersection defined by the first array and the second array, wherein each intersection of the first array and the second array defines a two-terminal resistive memory cell, said memory cell formed by a conductive path between said first and second electrodes.

公开(公告)号：US08552501B2

公开(公告)日：2013-10-08

申请号：US13447369

申请日：2012-04-16

申请人： Marius Orlowski ,  Andreas Wild

发明人： Marius Orlowski ,  Andreas Wild

IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L31/0392

CPC分类号： H01L29/7854 ,  H01L29/66795 ,  H01L29/78687

摘要： A method of forming an inverted T shaped channel structure having a vertical channel portion and a horizontal channel portion for an Inverted T channel Field Effect Transistor ITFET device comprises semiconductor substrate, a first layer of a first semiconductor material over the semiconductor substrate and a second layer of a second semiconductor material over the first layer. The first and the second semiconductor materials are selected such that the first semiconductor material has a rate of removal which is less than a rate of removal of the second semiconductor material.

摘要翻译： 形成具有用于反向T沟道场效应晶体管ITFET器件的垂直沟道部分和水平沟道部分的反向T形沟道结构的方法包括半导体衬底，半导体衬底上的第一半导体材料的第一层和第二层 在第一层上的第二半导体材料。 选择第一和第二半导体材料，使得第一半导体材料具有小于除去第二半导体材料的速率的去除速率。

公开(公告)号：US08202798B2

公开(公告)日：2012-06-19

申请号：US12675242

申请日：2007-09-20

申请人： Greg Braeckelmann ,  Hisao Kawasaki ,  Marius Orlowski ,  Emmanuel Petitprez

发明人： Greg Braeckelmann ,  Hisao Kawasaki ,  Marius Orlowski ,  Emmanuel Petitprez

IPC分类号： H01L21/4763

CPC分类号： H01L21/76838 ,  H01L21/7682 ,  H01L21/76831 ,  H01L23/53223 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit comprising one or more dielectric layers the or each dielectric layer being provided with one or more interconnects wherein the interconnect comprises metallic atoms moving from a first region of the interconnect to a second region of the interconnect when a current flows, characterized in that the interconnect comprises a donor zone in the first region of the interconnect for providing metallic atoms in order to compensate for movement of atoms from the first region and a receptor zone at the second region of the interconnect for receiving metallic atoms in order to compensate for movement of atoms to the second region.

摘要翻译： 一种包括一个或多个电介质层的集成电路，其中或每个电介质层设置有一个或多个互连，其中互连包括当电流流动时从互连的第一区域移动到互连的第二区域的金属原子，其特征在于 互连件包括在互连的第一区域中的供体区域，用于提供金属原子，以便补偿来自第一区域的原子的移动以及用于接收金属原子的互连的第二区域处的受体区域，以便补偿运动 的原子到第二个区域。

公开(公告)号：US20100044762A1

公开(公告)日：2010-02-25

申请号：US12605556

申请日：2009-10-26

申请人： Marius Orlowski

发明人： Marius Orlowski

IPC分类号： H01L29/78 ,  H01L29/772

CPC分类号： H01L29/78684 ,  H01L29/66818 ,  H01L29/785

摘要： A non-planar semiconductor device (10) starts with a silicon fin (42). A source of germanium (e.g. 24, 26, 28, 30, 32) is provided to the fin (42). Some embodiments may use deposition to provide germanium; some embodiments may use ion implantation (30) to provide germanium; other methods may also be used to provide germanium. The fin (42) is then oxidized to form a silicon germanium channel region in the fin (36). In some embodiments, the entire fin (42) is transformed from silicon to silicon germanium. One or more fins (36) may be used to form a non-planar semiconductor device, such as, for example, a FINFET, MIGFET, Tri-gate transistor, or multi-gate transistor.

摘要翻译： 非平面半导体器件（10）从硅片（42）开始。 将锗源（例如24,26,28,30,32）提供给翅片（42）。 一些实施例可以使用沉积来提供锗; 一些实施例可以使用离子注入（30）来提供锗; 也可以使用其它方法来提供锗。 然后将翅片（42）氧化以在翅片（36）中形成硅锗通道区域。 在一些实施例中，整个鳍（42）从硅转变为硅锗。 可以使用一个或多个翅片（36）来形成非平面半导体器件，例如FINFET，MIGFET，三栅极晶体管或多栅极晶体管。