公开(公告)号：US20130117513A1

公开(公告)日：2013-05-09

申请号：US13290702

申请日：2011-11-07

申请人： Mark A. Brittain ,  John Steven Dodson ,  Benjiman L. Goodman ,  Stephen J. Powell ,  Eric E. Retter ,  Jeffrey A. Stuecheli

发明人： Mark A. Brittain ,  John Steven Dodson ,  Benjiman L. Goodman ,  Stephen J. Powell ,  Eric E. Retter ,  Jeffrey A. Stuecheli

IPC分类号： G06F12/14

CPC分类号： G06F13/1626 ,  G06F13/16

摘要： Techniques for handling queuing of memory accesses prevent passing excessive requests that implicate a region of memory subject to a high latency memory operation, such as a memory refresh operation, memory scrubbing or an internal bus calibration event, to a re-order queue of a memory controller. The memory controller includes a queue for storing pending memory access requests, a re-order queue for receiving the requests, and a control logic implementing a queue controller that determines if there is a collision between a received request and an ongoing high-latency memory operation. If there is a collision, then transfer of the request to the re-order queue may be rejected outright, or a count of existing queued operations that collide with the high latency operation may be used to determine if queuing the new request will exceed a threshold number of such operations.

摘要翻译： 用于处理存储器访问排队的技术防止传递过多的请求，这些请求涉及存储器的区域，这些存储器受到诸如存储器刷新操作，存储器擦除或内部总线校准事件的高等待时间存储器操作到存储器的重新排序队列 控制器。 存储器控制器包括用于存储未决存储器访问请求的队列，用于接收请求的重新排序队列，以及实现队列控制器的控制逻辑，该队列控制器确定接收到的请求和正在进行的高延迟存储器操作之间是否存在冲突 。 如果存在冲突，则将请求转发到重新排序队列可能被直接拒绝，或者可能使用与高等待时间操作相冲突的现有排队操作的计数来确定新请求的队列是否将超过阈值 此类操作的数量。

公开(公告)号：US09632954B2

公开(公告)日：2017-04-25

申请号：US13290702

申请日：2011-11-07

申请人： Mark A. Brittain ,  John Steven Dodson ,  Benjiman L. Goodman ,  Stephen J. Powell ,  Eric E. Retter ,  Jeffrey A. Stuecheli

发明人： Mark A. Brittain ,  John Steven Dodson ,  Benjiman L. Goodman ,  Stephen J. Powell ,  Eric E. Retter ,  Jeffrey A. Stuecheli

IPC分类号： G06F12/00 ,  G06F13/16

CPC分类号： G06F13/1626 ,  G06F13/16

摘要： Techniques for handling queuing of memory accesses prevent passing excessive requests that implicate a region of memory subject to a high latency memory operation, such as a memory refresh operation, memory scrubbing or an internal bus calibration event, to a re-order queue of a memory controller. The memory controller includes a queue for storing pending memory access requests, a re-order queue for receiving the requests, and a control logic implementing a queue controller that determines if there is a collision between a received request and an ongoing high-latency memory operation. If there is a collision, then transfer of the request to the re-order queue may be rejected outright, or a count of existing queued operations that collide with the high latency operation may be used to determine if queuing the new request will exceed a threshold number of such operations.

公开(公告)号：US08539146B2

公开(公告)日：2013-09-17

申请号：US13305200

申请日：2011-11-28

申请人： Mark A. Brittain ,  John Steven Dodson ,  Benjiman L. Goodman ,  Stephen J. Powell ,  Jeffrey A. Stuecheli

发明人： Mark A. Brittain ,  John Steven Dodson ,  Benjiman L. Goodman ,  Stephen J. Powell ,  Jeffrey A. Stuecheli

IPC分类号： G06F12/00

CPC分类号： G11C11/40615 ,  G06F13/1694 ,  Y02D10/14

摘要： A method for performing refresh operations on a rank of memory devices is disclosed. After the completion of a memory operation, a determination is made whether or not a refresh backlog count value is less than a predetermined value and the rank of memory devices is being powered down. If the refresh backlog count value is less than the predetermined value and the rank of memory devices is being powered down, an Idle Count threshold value is set to a maximum value such that a refresh operation will be performed after a maximum delay time. If the refresh backlog count value is not less than the predetermined value or the rank of memory devices is not in a powered down state, the Idle Count threshold value is set based on the slope of an Idle Delay Function such that a refresh operation will be performed accordingly.

摘要翻译： 公开了一种用于在一级存储器件上执行刷新操作的方法。 在完成存储器操作之后，确定刷新积压计数值是否小于预定值，并且存储器件的等级被断电。 如果刷新积压计数值小于预定值并且存储器件的等级被断电，则将空闲计数阈值设置为最大值，使得将在最大延迟时间之后执行刷新操作。 如果刷新积压计数值不小于预定值或存储器件的等级不处于掉电状态，则基于空闲延迟功能的斜率来设置空闲计数阈值，使得刷新操作将 相应地执行。

公开(公告)号：US20130138878A1

公开(公告)日：2013-05-30

申请号：US13305200

申请日：2011-11-28

申请人： Mark A. Brittain ,  John Steven Dodson ,  Benjiman L. Goodman ,  Stephen J. Powell ,  Jeffrey A. Stuecheli

发明人： Mark A. Brittain ,  John Steven Dodson ,  Benjiman L. Goodman ,  Stephen J. Powell ,  Jeffrey A. Stuecheli

IPC分类号： G06F12/00

CPC分类号： G11C11/40615 ,  G06F13/1694 ,  Y02D10/14

摘要： A method for performing refresh operations on a rank of memory devices is disclosed. After the completion of a memory operation, a determination is made whether or not a refresh backlog count value is less than a predetermined value and the rank of memory devices is being powered down. If the refresh backlog count value is less than the predetermined value and the rank of memory devices is being powered down, an Idle Count threshold value is set to a maximum value such that a refresh operation will be performed after a maximum delay time. If the refresh backlog count value is not less than the predetermined value or the rank of memory devices is not in a powered down state, the Idle Count threshold value is set based on the slope of an Idle Delay Function such that a refresh operation will be performed accordingly.

摘要翻译： 公开了一种用于在一级存储器件上执行刷新操作的方法。 在完成存储器操作之后，确定刷新积压计数值是否小于预定值，并且存储器件的等级被断电。 如果刷新积压计数值小于预定值并且存储器件的等级被断电，则将空闲计数阈值设置为最大值，使得将在最大延迟时间之后执行刷新操作。 如果刷新积压计数值不小于预定值或存储器件的等级不处于掉电状态，则基于空闲延迟功能的斜率来设置空闲计数阈值，使得刷新操作将 相应地执行。

公开(公告)号：US06711652B2

公开(公告)日：2004-03-23

申请号：US09885999

申请日：2001-06-21

申请人： Ravi Kumar Arimilli ,  John Steven Dodson ,  James Stephen Fields, Jr.

发明人： Ravi Kumar Arimilli ,  John Steven Dodson ,  James Stephen Fields, Jr.

IPC分类号： G06F1200

CPC分类号： G06F12/0813

摘要： A non-uniform memory access (NUMA) computer system includes a remote node coupled by a node interconnect to a home node including a home system memory. The remote node includes a plurality of snoopers coupled to a local interconnect. The plurality of snoopers includes a cache that caches a cache line corresponding to but modified with respect to data resident in the home system memory. The cache has a cache controller that issues a deallocate operation on the local interconnect in response to deallocating the modified cache line. The remote node further includes a node controller, coupled between the local interconnect and the node interconnect, that transmits the deallocate operation to the home node with an indication of whether or not a copy of the cache line remains in the remote node following the deallocation. In this manner, the local memory directory associated with the home system memory can be updated to precisely reflect which nodes hold a copy of the cache line.

摘要翻译： 非均匀存储器访问（NUMA）计算机系统包括通过节点互连耦合到包括归属系统存储器的家庭节点的远程节点。 远程节点包括耦合到本地互连的多个窥探者。 多个窥探器包括高速缓存，其缓存对于相对于驻留在本地系统存储器中的数据而被修改的高速缓存线。 高速缓存具有缓存控制器，其响应于释放修改的高速缓存线而在本地互连上发出释放操作。 远程节点还包括耦合在本地互连和节点互连之间的节点控制器，其将取消分配操作发送到家庭节点，并指示在解除分配之后高速缓存行的副本是否保留在远程节点中。 以这种方式，可以更新与家庭系统存储器相关联的本地存储器目录，以精确地反映哪些节点保存高速缓存行的副本。

公开(公告)号：US06704843B1

公开(公告)日：2004-03-09

申请号：US09696890

申请日：2000-10-26

申请人： Ravi K. Arimilli ,  John Steven Dodson ,  James Stephen Fields, Jr. ,  Guy Lynn Guthrie

发明人： Ravi K. Arimilli ,  John Steven Dodson ,  James Stephen Fields, Jr. ,  Guy Lynn Guthrie

IPC分类号： G06F1208

CPC分类号： G06F12/0831

摘要： System bus snoopers within a multiprocessor system in which dynamic application sequence behavior information is maintained within cache directories append the dynamic application sequence behavior information for the target cache line to their snoop responses. The system controller, which may also maintain dynamic application sequence behavior information in a history directory, employs the available dynamic application sequence behavior information to append “hints” to the combined response, appends the concatenated dynamic application sequence behavior information to the combined response, or both. Either the hints or the dynamic application sequence behavior information may be employed by the bus master and other snoopers in cache management.

摘要翻译： 在多处理器系统内的系统总线监听器，其中动态应用程序行为信息保存在高速缓存目录中，将目标缓存行的动态应用程序序列行为信息附加到其监听响应。 也可以在历史目录中维护动态应用序列行为信息的系统控制器使用可用的动态应用序列行为信息来向组合响应附加“提示”，将连接的动态应用序列行为信息附加到组合响应，或 都。 在高速缓存管理中，总线主控和其他侦听器可以使用提示或动态应用序列行为信息。

公开(公告)号：US06662275B2

公开(公告)日：2003-12-09

申请号：US09782578

申请日：2001-02-12

申请人： Ravi Kumar Arimilli ,  John Steven Dodson ,  Guy Lynn Guthrie

发明人： Ravi Kumar Arimilli ,  John Steven Dodson ,  Guy Lynn Guthrie

IPC分类号： G06F1208

CPC分类号： G06F12/0811 ,  G06F12/0848

摘要： A method of maintaining coherency in a cache hierarchy of a processing unit of a computer system, wherein the upper level (L1) cache includes a split instruction/data cache. In one implementation, the L1 data cache is store-through, and each processing unit has a lower level (L2) cache. When the lower level cache receives a cache operation requiring invalidation of a program instruction in the L1 instruction cache (i.e., a store operation or a snooped kill), the L2 cache sends an invalidation transaction (e.g., icbi) to the instruction cache. The L2 cache is fully inclusive of both instructions and data. In another implementation, the L1 data cache is write-back, and a store address queue in the processor core is used to continually propagate pipelined address sequences to the lower levels of the memory hierarchy, i.e., to an L2 cache or, if there is no L2 cache, then to the system bus. If there is no L2 cache, then the cache operations may be snooped directly against the L1 instruction cache.

公开(公告)号：US06662216B1

公开(公告)日：2003-12-09

申请号：US08839478

申请日：1997-04-14

申请人： Ravi Kumar Arimilli ,  John Steven Dodson ,  Jerry Don Lewis

发明人： Ravi Kumar Arimilli ,  John Steven Dodson ,  Jerry Don Lewis

IPC分类号： G06F1516

CPC分类号： G06F11/349 ,  G06F12/0831 ,  G06F2201/885

摘要： According to a first aspect of the present invention, a data processing system is provided that includes a communication network to which multiple devices are coupled. A first of the multiple devices includes a number of requestors (or queues), which are each permanently assigned a respective one of a number of unique tags. In response to a communication request by a requestor within the first device, a tag assigned to the requestor is transmitted on the communication network in conjunction with the requested communication transaction. According to a second aspect of the present invention, a data processing system includes a cache having a cache directory. A status indication indicative of the status of at least one of a plurality of data entries in the cache is stored in the cache directory. In response to receipt of a cache operation request, a determination is made whether to update the status indication. In response to the determination that the status indication is to be updated, the status indication is copied into a shadow register and updated. The status indication is then written back into the cache directory at a later time. The shadow register thus serves as a virtual cache controller queue that dynamically mimics a cache directory entry without functional latency.

摘要翻译： 根据本发明的第一方面，提供一种数据处理系统，其包括多个设备耦合到的通信网络。 多个设备中的第一个包括多个请求者（或队列），每个请求者（或队列）被永久地分配多个唯一标签中的相应的一个。 响应于第一设备内的请求者的通信请求，分配给请求者的标签与所请求的通信事务一起在通信网络上发送。 根据本发明的第二方面，数据处理系统包括具有高速缓存目录的高速缓存。 指示高速缓存中的多个数据条目中的至少一个的状态的状态指示被存储在高速缓存目录中。 响应于接收到高速缓存操作请求，确定是否更新状态指示。 响应于要更新状态指示的确定，状态指示被复制到影子寄存器并被更新。 状态指示随后被写回缓存目录。 因此，影子寄存器用作虚拟高速缓存控制器队列，其动态地模拟高速缓存目录条目而没有功能延迟。

公开(公告)号：US06631450B1

公开(公告)日：2003-10-07

申请号：US09696889

申请日：2000-10-26

申请人： Ravi K. Arimilli ,  John Steven Dodson ,  James Stephen Fields, Jr. ,  Guy Lynn Guthrie

发明人： Ravi K. Arimilli ,  John Steven Dodson ,  James Stephen Fields, Jr. ,  Guy Lynn Guthrie

IPC分类号： G06F1208

CPC分类号： G06F12/0831

摘要： System bus masters within a multiprocessor system in which dynamic application sequence behavior information is maintained within cache directories append the historical access information for the target cache line to their requests. Snoopers and/or the system controller, which may also maintain dynamic application sequence behavior information in a history directory, employ the appended access information for cache management.

摘要翻译： 多处理器系统内的系统总线主机，其中动态应用程序行为信息保存在高速缓存目录中，将目标缓存行的历史访问信息追加到其请求中。 也可以在历史目录中维护动态应用序列行为信息的侦听器和/或系统控制器采用附加的访问信息进行高速缓存管理。

公开(公告)号：US06629214B1

公开(公告)日：2003-09-30

申请号：US09437186

申请日：1999-11-09

申请人： Ravi Kumar Arimilli ,  Lakshminarayana Baba Arimilli ,  John Steven Dodson ,  Guy Lynn Guthrie ,  William John Starke

发明人： Ravi Kumar Arimilli ,  Lakshminarayana Baba Arimilli ,  John Steven Dodson ,  Guy Lynn Guthrie ,  William John Starke

IPC分类号： G06F1300

CPC分类号： G06F12/0815 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3857

摘要： A multiprocessor data processing system requires careful management to maintain cache coherency. Conventional systems using a MESI approach sacrifice some performance with inefficient lock-acquisition and lock-retention techniques. The disclosed system provides additional cache states, indicator bits, and lock-acquisition routines to improve cache performance. The additional cache states allow cache state transition sequences to be optimized. In particular, the claimed system and method provides that a given processor, after acquiring a lock or reservation to a given cache line, will keep the lock, to make successive modifications to the cache line, instead of releasing it to other processors after making only one modification. By doing so, the overhead typically required to acquire a lock before making any cache line modification is eliminated for successive modifications.

摘要翻译： 多处理器数据处理系统需要仔细管理以保持高速缓存一致性。 使用MESI方法的传统系统通过低效的锁定采集和锁定保留技术来牺牲一些性能。 所公开的系统提供附加的高速缓存状态，指示符位和锁定采集例程以提高高速缓存性能。 额外的缓存状态允许优化缓存状态转换序列。 特别地，所要求保护的系统和方法规定，给定的处理器在获得对给定高速缓存行的锁定或预留之后将保持锁定以对缓存行进行连续修改，而不是在仅进行制作之后将其释放到其他处理器 一个修改。 通过这样做，为了连续修改，消除了在进行任何高速缓存行修改之前获取锁的通常需要的开销。