公开(公告)号：US20060156100A1

公开(公告)日：2006-07-13

申请号：US11023731

申请日：2004-12-28

申请人： Mark Boike ,  Seshagiri Kalluri ,  Vijayanand Angarai ,  David Brantley ,  Scott Beeker

发明人： Mark Boike ,  Seshagiri Kalluri ,  Vijayanand Angarai ,  David Brantley ,  Scott Beeker

IPC分类号： G01R31/28

CPC分类号： G01R31/318572

摘要： An apparatus and method are disclosed for testing a hard macro that is embedded in a system on a chip (SOC) that is included in an integrated circuit chip. The SOC includes the hard macro. A logic design and operation of the hard macro are unknown. A test wrapper is embedded in the SOC. The test wrapper includes a scan chain. The test wrapper surrounds inputs and outputs of the hard macro. The test wrapper receives a known test data pattern in the scan chain that is included in the test wrapper. The hard macro receives from the test wrapper a set of non-test standard SOC inputs when the SOC is not in a test mode and receives the known test data pattern when the SOC is in the test mode. The hard macro generates a set of outputs in response to the inputs. The hard macro is tested utilizing the known test data pattern.

公开(公告)号：US06622154B1

公开(公告)日：2003-09-16

申请号：US09467939

申请日：1999-12-21

申请人： Naoki Hayashi ,  Vijayanand Angarai

发明人： Naoki Hayashi ,  Vijayanand Angarai

IPC分类号： G06F752

CPC分类号： G06F7/5338

摘要： In hardware multipliers, the generation of partial products is a necessary step in the process known to the art for efficient production of a final product. A way to increase the speed of hardware multipliers is through the use of the Booth algorithm. The alternate Booth partial product generation for hardware multipliers of the present invention is directed to a method and apparatus for eliminating the encoding of the bits of the multiplier prior to entering the partial product generating cell of the present invention which may result in less hardware and increased speed.

摘要翻译： 在硬件乘法器中，部分产品的产生是本领域已知的用于有效生产最终产品的过程中的必要步骤。 通过使用布斯算法，提高硬件乘法器速度的一种方法。 本发明的用于硬件乘法器的替代Booth部分乘积生成涉及一种用于在进入本发明的部分乘积生成单元之前消除乘数的比特的编码的方法和装置，这可能导致较少的硬件和增加 速度。

公开(公告)号：US20100058039A1

公开(公告)日：2010-03-04

申请号：US12204769

申请日：2008-09-04

申请人： Vijayanand Angarai ,  Michelle Y. Che ,  Asheesh Kashyap ,  Tracy Nguyen

发明人： Vijayanand Angarai ,  Michelle Y. Che ,  Asheesh Kashyap ,  Tracy Nguyen

IPC分类号： G06F9/30

CPC分类号： G06F9/321 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/325 ,  G06F9/3804 ,  G06F9/382 ,  G06F9/3842

摘要： A next program counter (PC) value generator. The next PC value generator includes a discontinuity decoder that is provide to detect a discontinuity instruction among a plurality of instructions and a tight loop decoder that is provide to: a) detect a tight loop instruction, and b) provide a tight loop instruction target address. The next PC value generator further includes a next PC value logic having a plurality of inputs: a first input coupled to an output of the discontinuity decoder, and a second input coupled to an output of the tight loop decoder. The next PC value logic provides as an output, without a stall, a control signal that a next PC value is to be loaded with the tight loop instruction target address if: the discontinuity decoder detects a discontinuity instruction, and the tight loop decoder detects a tight loop instruction.

摘要翻译： 下一个程序计数器（PC）值生成器。 下一个PC值生成器包括：不连续解码器，用于检测多个指令中的不连续指令;以及紧密环路解码器，其提供用于：a）检测紧密指令，以及b）提供紧密指令目标地址 。 下一个PC值产生器还包括具有多个输入的下一个PC值逻辑：耦合到不连续解码器的输出的第一输入和耦合到紧循环解码器的输出的第二输入。 如果：不连续解码器检测到不连续指令，则下一个PC值逻辑提供无延迟的下一个PC值将被加载紧密指令目标地址的输出作为输出，并且紧密环路解码器检测到 紧循环指令。

公开(公告)号：US08095781B2

公开(公告)日：2012-01-10

申请号：US12204769

申请日：2008-09-04

申请人： Vijayanand Angarai ,  Michelle Y. Che ,  Asheesh Kashyap ,  Tracy Nguyen

发明人： Vijayanand Angarai ,  Michelle Y. Che ,  Asheesh Kashyap ,  Tracy Nguyen

IPC分类号： G06F9/35 ,  G06F9/355

CPC分类号： G06F9/321 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/325 ,  G06F9/3804 ,  G06F9/382 ,  G06F9/3842

摘要： A next program counter (PC) value generator. The next PC value generator includes a discontinuity decoder that is provide to detect a discontinuity instruction among a plurality of instructions and a tight loop decoder that is provide to: a) detect a tight loop instruction, and b) provide a tight loop instruction target address. The next PC value generator further includes a next PC value logic having a plurality of inputs: a first input coupled to an output of the discontinuity decoder, and a second input coupled to an output of the tight loop decoder. The next PC value logic provides as an output, without a stall, a control signal that a next PC value is to be loaded with the tight loop instruction target address if: the discontinuity decoder detects a discontinuity instruction, and the tight loop decoder detects a tight loop instruction.

摘要翻译： 下一个程序计数器（PC）值生成器。 下一个PC值生成器包括：不连续解码器，用于检测多个指令中的不连续指令;以及紧密环路解码器，其提供用于：a）检测紧密指令，以及b）提供紧密指令目标地址 。 下一个PC值产生器还包括具有多个输入的下一个PC值逻辑：耦合到不连续解码器的输出的第一输入和耦合到紧循环解码器的输出的第二输入。 如果：不连续解码器检测到不连续指令，则下一个PC值逻辑提供无延迟的下一个PC值将被加载紧密指令目标地址的输出作为输出，并且紧密环路解码器检测到 紧循环指令。