公开(公告)号：US20060195680A1

公开(公告)日：2006-08-31

申请号：US11406031

申请日：2006-04-18

申请人： Mark Check ,  Brian Moore ,  Timothy Slegel

发明人： Mark Check ,  Brian Moore ,  Timothy Slegel

IPC分类号： G06F9/44

CPC分类号： G06F9/30145 ,  G06F9/30167

摘要： A computer machine instruction is fetched and executed, the machine instruction having a signed field value wherein the signed field value comprises contiguous bit positions 1-N consisting of a contiguous most significant value contiguous with a contiguous embedded sign field, the embedded sign field contiguous with a contiguous least significant value. Preferably, the sign field is one bit, the contiguous most significant value comprises bit position N and the least significant value comprises bit position 1 wherein N is the least significant bit of the most significant value.

摘要翻译： 取出并执行计算机机器指令，该机器指令具有带符号的字段值，其中，有符号的字段值包括由与邻接的嵌入符号字段相邻的连续最高有效值组成的连续位位置1 -N，与 连续的最低有效值。 优选地，符号字段是一位，连续的最高有效值包括比特位置N，最低有效值包括比特位置1，其中N是最高有效值的最低有效位。

公开(公告)号：US20050278507A1

公开(公告)日：2005-12-15

申请号：US10403417

申请日：2003-03-28

申请人： Mark Check ,  Brian Moore ,  Timothy Slegel

发明人： Mark Check ,  Brian Moore ,  Timothy Slegel

IPC分类号： G06F9/30

CPC分类号： G06F9/30145 ,  G06F9/30167

摘要： A computer architecture that provides the definition of a 20 bit signed displacement value used to form the operand storage address.

摘要翻译： 提供用于形成操作数存储地址的20位有符号位移值的定义的计算机体系结构。

公开(公告)号：US20050216713A1

公开(公告)日：2005-09-29

申请号：US10809749

申请日：2004-03-25

申请人： Brian Prasky ,  Mark Check ,  Bruce Giamei ,  Timothy Slegel

发明人： Brian Prasky ,  Mark Check ,  Bruce Giamei ,  Timothy Slegel

IPC分类号： G06F9/00 ,  G06F9/30 ,  G06F9/318 ,  G06F9/38

CPC分类号： G06F9/30145 ,  G06F9/30181 ,  G06F9/3806

摘要： Disclosed is a method and apparatus providing the capability to prevent particular branches from being written into the BTB, thereby making them non-predictable. By making certain branches only detectable at decode time frame, branch prediction can completely run asynchronous of decode. By allowing branch prediction logic to cover as wide a range of branches as possible, the efficiency of fetching of branch targets way before the branch itself achieves a higher level of precision. This increased level of precision eliminates pipeline stalls between branches and targets where prior concerns of creating data integrity within the pipeline of a microprocessor existed.

摘要翻译： 公开了提供防止特定分支被写入BTB的能力的方法和装置，从而使它们不可预测。 通过使某些分支仅在解码时间帧可检测到，分支预测可以完全执行解码的异步。 通过允许分支预测逻辑覆盖尽可能广泛的分支范围，在分支本身实现更高精度之前，提取分支目标的效率。 这种增加的精度水平消除了分支和目标之间的流水线停顿，其中在微处理器管线内存在创建数据完整性的事先担心。

公开(公告)号：US20070233918A1

公开(公告)日：2007-10-04

申请号：US11761154

申请日：2007-06-11

申请人： Mark Check ,  Bernard Drerup ,  Michael Grassi

发明人： Mark Check ,  Bernard Drerup ,  Michael Grassi

IPC分类号： G06F13/00

CPC分类号： G06F13/36

摘要： A communications bus for a digital device includes a credit-based flow control mechanism, in which a sending component maintains a local record of its credits. Credits are returned to the sender by pulsing a single-bit credit return line. A separate mechanism provides a count of available credits from the receiver, the separate mechanism not necessarily being current. The local record is compared to the count of credits from the separate mechanism over a pre-determined time interval, failure of the two values to agree at any time during the interval indicating a probable credit discrepancy. A credit discrepancy is confirmed, preferably by suspending certain bus activity for a sufficiently long period to account for any delay in propagating credit value changes, and re-comparing the values. Preferably, the bus communicates between internal components of an integrated circuit chip

摘要翻译： 用于数字设备的通信总线包括基于信用的流量控制机制，其中发送组件保持其信用的本地记录。 通过脉冲单位信用回报线将积分返还给发件人。 单独的机制提供来自接收器的可用信用的计数，单独的机制不一定是当前的。 将本地记录与预定时间间隔内的单独机制的信用计数进行比较，两个值在表示可能的信用差异的间隔期间的任何时间失败。 确认信用差异，最好是通过暂停一段长时间的公共汽车活动来解决传播信用额度变化的任何延误，并重新比较价值。 优选地，总线在集成电路芯片的内部部件之间进行通信

公开(公告)号：US20060174040A1

公开(公告)日：2006-08-03

申请号：US11047547

申请日：2005-01-31

申请人： Mark Check ,  Bernard Drerup ,  Michael Grassi

发明人： Mark Check ,  Bernard Drerup ,  Michael Grassi

IPC分类号： G06F3/00 ,  G06F13/36

CPC分类号： G06F13/36

摘要： A communications bus for a digital device includes a credit-based flow control mechanism, in which a sending component maintains a local record of its credits. Credits are returned to the sender by pulsing a single-bit credit return line. A separate mechanism provides a count of available credits from the receiver, the separate mechanism not necessarily being current. The local record is compared to the count of credits from the separate mechanism over a pre-determined time interval, failure of the two values to agree at any time during the interval indicating a probable credit discrepancy. A credit discrepancy is confirmed, preferably by suspending certain bus activity for a sufficiently long period to account for any delay in propagating credit value changes, and re-comparing the values. Preferably, the bus communicates between internal components of an integrated circuit chip

摘要翻译： 用于数字设备的通信总线包括基于信用的流量控制机制，其中发送组件保持其信用的本地记录。 通过脉冲单位信用回报线将积分返还给发件人。 单独的机制提供来自接收器的可用信用的计数，单独的机制不一定是当前的。 将本地记录与预先确定的时间间隔内的单独机制的信用计数进行比较，两个值在表示可能的信用差异的间隔期间的任何时间失败。 确认信用差异，最好是通过暂停一段长时间的公共汽车活动来解决传播信用额度变化的任何延误，并重新比较价值。 优选地，总线在集成电路芯片的内部部件之间进行通信

公开(公告)号：US20060174158A1

公开(公告)日：2006-08-03

申请号：US11047522

申请日：2005-01-31

申请人： Mark Check ,  Bernard Drerup ,  Michael Grassi

发明人： Mark Check ,  Bernard Drerup ,  Michael Grassi

IPC分类号： G06F11/00

CPC分类号： G06F13/4022

摘要： An integrated circuit chip includes multiple functional components and a central interconnect (CI) module. Each functional component communicates with the CI module via a respective internal bus sharing a common architecture which does not dictate any particular data alignment. The chip architecture defines an alignment mechanism within the CI module, which performs any required alignment of transmitted data. Alignment mechanism design parameters can be varied to accommodate different alignment domains of different functional components. Preferably, the common bus architecture supports multiple internal bus widths, the CI module performing any required bus width conversion. Preferably, for certain transactions not containing a data address, correct alignment is obtained by placing restrictions on transaction size and boundaries, and duplicating certain data on different alignment boundaries. The use of a common bus protocol and CI module having alignment capability streamlines the design process and reduces the overhead of alignment conversion.

摘要翻译： 集成电路芯片包括多个功能组件和中央互连（CI）模块。 每个功能组件通过共享具有不规定任何特定数据对准的公共架构的相应内部总线与CI模块通信。 芯片架构定义了CI模块内的对准机制，其执行传输数据的任何所需的对准。 对准机构设计参数可以变化以适应不同功能组件的不同对准域。 优选地，公共总线架构支持多个内部总线宽度，CI模块执行任何所需的总线宽度转换。 优选地，对于不包含数据地址的某些事务，通过对事务大小和边界进行限制并且在不同的对准边界上复制某些数据来获得正确的对准。 使用具有对准能力的公共总线协议和CI模块简化了设计过程并减少了对准转换的开销。

公开(公告)号：US20060174050A1

公开(公告)日：2006-08-03

申请号：US11047549

申请日：2005-01-31

申请人： Sundeep Chadha ,  Mark Check ,  Bernard Drerup ,  Michael Grassi

发明人： Sundeep Chadha ,  Mark Check ,  Bernard Drerup ,  Michael Grassi

IPC分类号： G06F13/36

CPC分类号： G06F13/4059

摘要： An integrated circuit chip includes multiple functional components and a central interconnect module providing communication among the functional components. The central interconnect module includes a buffer which is shared by the sending and receiving components. Preferably, some components perform different functions and communicate with the central interconnect via a common architectural interface. Preferably, each sender is allocated respective credits representing ability of the receiver to receive data (e.g., available buffer space), and the sender can transmit data if it has credits. Credits are decremented when the sender sends data, and returned by the receiver when is again able to receive. The use of a common central interconnect module with a shared buffer reduces buffer requirements and provides a low-overhead path for transferring data within the integrated circuit chip.

摘要翻译： 集成电路芯片包括多个功能部件和提供功能部件之间的通信的中央互连模块。 中央互连模块包括由发送和接收组件共享的缓冲器。 优选地，一些组件执行不同的功能并且经由公共架构接口与中央互连通信。 优选地，每个发送者被分配相应的信用表示接收器接收数据的能力（例如，可用的缓冲区空间），并且如果发送者具有信用则发送者可以发送数据。 当发送方发送数据时，信用减少，当接收者再次接收时返回。 共享缓冲区使用共同的中央互连模块减少了缓冲区的需求，并为集成电路芯片内的数据传输提供了低开销的路径。

公开(公告)号：US20050246507A1

公开(公告)日：2005-11-03

申请号：US10834637

申请日：2004-04-29

申请人： Fadi Busaba ,  Steven Carlough ,  Mark Check ,  Christopher Krygowski ,  John Rell ,  Frank Tanzi

发明人： Fadi Busaba ,  Steven Carlough ,  Mark Check ,  Christopher Krygowski ,  John Rell ,  Frank Tanzi

IPC分类号： G06F9/30 ,  G06F9/312 ,  G06F9/315 ,  G06F9/38 ,  G06F12/00 ,  G06F12/08

CPC分类号： G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/3816 ,  G06F9/3824 ,  G06F12/0886

摘要： A method of pre-aligning data for storage during instruction execution improves performance by eliminating the cycles otherwise required for data alignment. The method can convert data between ASCII and Packed Decimal format, and between Unicode Basic Latin and Packed Decimal format. Conversion to Packed Decimal format is needed for decimal hardware in a microprocessor designed to generate decimal results. Converting from Packed Decimal to ASCII and Unicode Basic Latin is necessary to report Decimal Arithmetic results in a required format for the application program. To further improve performance, all available write ports in the fixed point unit (FXU) are utilized to reduce the number of cycles necessary to store results. To prevent data fetching of the unused destination data from slowing down instruction execution, the destination locations are tested for storage access exceptions, but the data for these operands are not actually fetched. A single read request from the FXU to the operand buffers effectively reads the entire destination address (up to 8 double-words of data) in a single cycle.

摘要翻译： 在指令执行期间预先对准用于存储的数据的方法通过消除数据对准所需的周期来提高性能。 该方法可以在ASCII和Packed Decimal格式之间以及Unicode Basic Latin和Packed Decimal格式之间转换数据。 转换为打包十进制硬件需要十进制格式，用于生成十进制结果的微处理器。 从包装十进制转换为ASCII和Unicode基本拉丁文需要以应用程序所需的格式报告十进制算术结果。 为了进一步提高性能，利用固定点单元（FXU）中的所有可用写入端口来减少存储结果所需的周期数。 为了防止数据获取未使用的目标数据缓慢的指令执行，目标位置被测试存储访问异常，但是这些操作数的数据实际上并没有被提取。 从FXU到操作数缓冲区的单个读取请求在单个周期中有效读取整个目标地址（最多8个双字的数据）。

公开(公告)号：US20070067545A1

公开(公告)日：2007-03-22

申请号：US11553500

申请日：2006-10-27

申请人： Mark Check ,  Bernard Drerup ,  Michael Grassi

发明人： Mark Check ,  Bernard Drerup ,  Michael Grassi

IPC分类号： G06F13/36

CPC分类号： G06F13/36

摘要： A communications bus for a digital device includes a credit-based flow control mechanism, in which a sending component maintains a local record of its credits. Credits are returned to the sender by pulsing a single-bit credit return line. A separate mechanism provides a count of available credits from the receiver, the separate mechanism not necessarily being current. The local record is compared to the count of credits from the separate mechanism over a pre-determined time interval, failure of the two values to agree at any time during the interval indicating a probable credit discrepancy. A credit discrepancy is confirmed, preferably by suspending certain bus activity for a sufficiently long period to account for any delay in propagating credit value changes, and re-comparing the values. Preferably, the bus communicates between internal components of an integrated circuit chip

公开(公告)号：US20060179182A1

公开(公告)日：2006-08-10

申请号：US11047548

申请日：2005-01-31

申请人： Sundeep Chadha ,  Mark Check ,  Bernard Drerup ,  Michael Grassi

发明人： Sundeep Chadha ,  Mark Check ,  Bernard Drerup ,  Michael Grassi

IPC分类号： G06F3/00

CPC分类号： G06F13/4059

摘要： A control mechanism for data bus communications employs channels to which bus transactions are assigned, each channel having independent flow control. The control mechanism enforces an ordering algorithm among channels, whereby at least some transactions may pass other transactions. Channel attributes are programmable to vary the ordering conditions. Preferably, each channel is allocated its own programmable buffer area. The control mechanism independently determines, for each channel, whether buffer space is available and enforces flow control independently for each channel accordingly. Flow control is preferably credit-based, credits representing buffer space or some other capacity of a receiver to receive data. Preferably, the flow control mechanism comprises a central interconnect module controlling internal communications of an integrated circuit chip.