-
公开(公告)号：US5703838A
公开(公告)日：1997-12-30
申请号：US602904
申请日：1996-02-16
Applicant: Mark S. Gorbics , Keith M. Roberts , Richard L. Sumner
Inventor： Mark S. Gorbics , Keith M. Roberts , Richard L. Sumner
CPC classification number: H03M1/0697 , G04F10/06 , H03K5/159 , H03M1/50 , H03M1/502
Abstract: A Vernier delay line interpolator provides a precision level smaller than a clock period by delaying a periodic pulse signal in a delay line which has equally time-spaced taps and a total delay that is a harmonic H greater than 1 of the pulse period. The taps of the delay line are latched and decoded to derive the fraction of the pulse period that has passed. When the interpolator is combined with a coarse counter, misalignment between their outputs is prevented by having the coarse counter count both edges of the periodic pulse signal so as to provide redundant bits between the counter and the interpolator. If the redundant bits are not equal, the counter output is corrected before it is combined with the output of the interpolator.
Abstract translation: 游标延迟线内插器通过延迟具有等间隔抽头的延迟线中的周期性脉冲信号和大于脉冲周期1的谐波H的总延迟来提供小于时钟周期的精度电平。 延迟线的抽头被锁存和解码，以导出已经过去的脉冲周期的分数。 当内插器与粗计数器组合时，通过使粗计数器计数周期性脉冲信号的两个边缘以便在计数器和内插器之间提供冗余位来防止它们的输出之间的对准。 如果冗余位不相等，则在与内插器的输出组合之前校正计数器输出。
-
公开(公告)号：US5838754A
公开(公告)日：1998-11-17
申请号：US814835
申请日：1997-03-11
Applicant: Mark S. Gorbics , Keith M. Roberts , Richard L. Sumner
Inventor： Mark S. Gorbics , Keith M. Roberts , Richard L. Sumner
CPC classification number: H03M1/0697 , G04F10/06 , H03K5/159 , H03M1/50 , H03M1/502
Abstract: A Vernier delay line interpolator provides a precision level smaller than a clock period by delaying a periodic pulse signal in a delay line which has equally time-spaced taps and a total delay that is a harmonic H greater than 1 of the pulse period. The taps of the delay line are latched and decoded to derive the fraction of the pulse period that has passed. When the interpolator is combined with a coarse counter, misalignment between their outputs is prevented by having the coarse counter count both edges of the periodic pulse signal so as to provide redundant bits between the counter and the interpolator. If the redundant bits are not equal, the counter output is corrected before it is combined with the output of the interpolator.
Abstract translation: 游标延迟线内插器通过延迟具有等间隔抽头的延迟线中的周期性脉冲信号和大于脉冲周期1的谐波H的总延迟来提供小于时钟周期的精度电平。 延迟线的抽头被锁存和解码，以导出已经过去的脉冲周期的分数。 当内插器与粗计数器组合时，通过使粗计数器计数周期性脉冲信号的两个边缘以便在计数器和内插器之间提供冗余位来防止它们的输出之间的对准。 如果冗余位不相等，则在与内插器的输出组合之前校正计数器输出。
-
公开(公告)号：US5835050A
公开(公告)日：1998-11-10
申请号：US735928
申请日：1996-10-23
Applicant: Keith M. Roberts
Inventor： Keith M. Roberts
CPC classification number: H03M1/188
Abstract: A multi-range analog-to-digital converter for encoding rundown times into a single channel of pulse width encoded data which may be conveyed to a remote equipment room over a single inexpensive, low quality digital cable. An input charge pulse is divided into multiple charge pulses and rundown times of the divided charge pulses are combined and encoded into a single channel of encoded data. A digital value representation of the input charge pulse is derived from the most accurate rundown times selected from the single channel of encoded data.
Abstract translation: 一种多范围模数转换器，用于将冗余时间编码为单个通道的脉冲宽度编码数据，可以通过单个廉价，低质量的数字电缆传送到远程机房。 输入充电脉冲被分成多个充电脉冲，分频充电脉冲的下降时间被组合并编码成编码数据的单个通道。 输入电荷脉冲的数字值表示从从编码数据的单个通道中选择的最精确的衰减时间导出。
-
-
Search Results
3
records
(took 0.027 seconds)
