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公开(公告)号：US5757875A
公开(公告)日：1998-05-26
申请号：US626161
申请日：1996-04-01
CPC分类号： G01D5/2457
摘要： A method for identifying a principal tooth in a series of teeth extending along at least a portion of a periphery of a rotatable object includes the steps of rotating the rotatable object, setting a counter to a predetermined value, measuring a first tooth in the series of teeth to obtain a first measurement, adding a qualifying value to the measurement to obtain a qualification measurement, measuring a second tooth in the series of teeth to obtain a second measurement, comparing the second measurement to the qualification measurement, and identifying the second tooth as the principal tooth when the second measurement exceeds the qualification measurement.
摘要翻译： 一种用于识别沿着可旋转物体的周边的至少一部分延伸的一系列齿中的主齿的方法包括以下步骤：使可旋转物体旋转，设定相对于预定值，测量该系列中的第一齿 以获得第一测量值，向测量值添加限定值以获得鉴定测量，测量所述一系列齿中的第二齿以获得第二测量，将所述第二测量与所述鉴定测量进行比较，以及将所述第二齿识别为 当第二次测量超过资格测量时的主齿。
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公开(公告)号：US5129078A
公开(公告)日：1992-07-07
申请号：US233786
申请日：1988-08-19
IPC分类号： G06F1/14 , G06F13/12 , G06F13/362 , G06F15/78
CPC分类号： G06F13/124
摘要： A system comprises a service processor and a plurality of operating units dependent on the service processor. The service processor responds to service requests from the operating units and services the operating units one at a time. A scheduler is responsible for assigning priority to the operating units and determining the order in which the service requests are handled. A register contains a value indicative of the operating unit currently being serviced and is under control of the scheduler. According to one aspect of the present invention the register is also under control of the service processor itself. Another register, under control of the service processor, is coupled to the scheduler to generate service requests thereto independent of the operating units. A memory addressable by the service processor stores data. The service processor is capable of generating addresses for the memory derived from the contents of the register indicative of the operating unit currently being serviced.
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公开(公告)号：US4942522A
公开(公告)日：1990-07-17
申请号：US234103
申请日：1988-08-19
摘要： A timer channel with multiple timer reference signals available to it which is capable of performing any input or output timer function with reference to any of the available reference signals. In addition, input timer functions may be related to the occurrence of output functions. For instance, the state of one timer reference may be captured automatically at a specified time referenced to another timer reference. Another feature of the invention provides for the creation of a time-out window for an input timer function through the use of a concurrent output function.
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4.发明授权Integrated circuit timer with multiple channels and dedicated service processor 失效多通道集成电路定时器和专用服务处理器
公开(公告)号：US4926319A
公开(公告)日：1990-05-15
申请号：US234104
申请日：1988-08-19
IPC分类号： G04G3/00 , G04G99/00 , G06F1/14 , G06F15/16 , G06F15/177
摘要： A timer system comprises multiple channels, each of which is capable of performing input and output timer functions referenced to any of a plurality of timer reference signals. In the preferred embodiment, sixteen independent channels are serviced by a processor dedicated to that purpose and each can perform capture and match functions referenced to either of two free-running counters.
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5.发明授权Integrated circuit timer with multiple channels and dedicated service processor 失效多通道集成电路定时器和专用服务处理器
公开(公告)号：US5204957A
公开(公告)日：1993-04-20
申请号：US954940
申请日：1992-09-30
摘要： A timer system comprises multiple channels, each of which is capable of performing input and output timer functions referenced to any of a plurality of timer reference signals. In the preferred embodiment, sixteen independent channels are serviced by a processor dedicated to that purpose and each can perform capture and match functions referenced to either of two free-running counters.
摘要翻译： 定时器系统包括多个通道，每个通道能够执行参考多个定时器参考信号中的任何一个的输入和输出定时器功能。 在优选实施例中，十六个独立信道由专用于该目的的处理器提供服务，并且每个可以执行参考两个自由运行计数器之一的捕获和匹配功能。
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6.发明授权Integrated circuit input/output processor having improved timer capability 失效具有改进的定时器能力的集成电路输入/输出处理器
公开(公告)号：US5634045A
公开(公告)日：1997-05-27
申请号：US555456
申请日：1995-11-13
申请人： Vernon B. Goler , Gary L. Miller , David Rivera
发明人： Vernon B. Goler , Gary L. Miller , David Rivera
CPC分类号： G06F15/78
摘要： Referring to FIGS. 1 and 2, I/O control modules (IOCMs 25-29) have channels which communicate by way of timer buses (71, 72) and pin/status buses (75-77). Channels (86, 87) are partitioned by each timer bus (71, 72) into separate blocks of channels (86, 87) which are provided with access to different timebase values from timebase channels (80, 81) by their respective timer bus (71, 72), so there is no loss of resolution because each channel in a timer bus block (e.g. 86) can concurrently receive the same timebase value from its corresponding timer bus (71). Pin/status buses (75-77) allow simultaneity of control among the channels (e.g. 58) coupled to the same pin/status bus (e.g. 76). Pin/status buses (75-77) and timer buses (71, 72) can be independently partitioned.
摘要翻译： 参见图 如图1和图2所示，I / O控制模块（IOCM 25-29）具有通过定时器总线（71,72）和引脚/状态总线（75-77）进行通信的通道。 信道（86,87）被每个定时器总线（71,72）划分成分离的信道块（86,87），它们通过它们各自的定时器总线（时钟基准信道（80,81））提供对不同时基值的访问 71，72），所以没有分辨率的损失，因为定时器总线块（例如86）中的每个通道可以从其对应的定时器总线（71）同时接收相同的时基值。 引脚/状态总线（75-77）允许在耦合到相同引脚/状态总线（例如76）的通道（例如58）之间同时进行控制。 引脚/状态总线（75-77）和定时器总线（71,72）可以独立分区。
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公开(公告)号：US5631853A
公开(公告)日：1997-05-20
申请号：US556474
申请日：1995-11-13
申请人： Gary L. Miller , Vernon B. Goler , Thomas R. Toms
发明人： Gary L. Miller , Vernon B. Goler , Thomas R. Toms
CPC分类号： G06F1/14
摘要： Referring to FIGS. 2, 13, and 14, the tag value transferred by timebase select signals (50) indicates which timebase is presently available on timer bus (71). In one embodiment, each channel (61, 62, 80, 81, and 86) compares the tag value of the timebase select signals (50) with a user programmed tag value stored in a register portion (264). If the stored tag value matches the tag value being driven on the timebase select signals (50), then the match signal (263) is asserted to indicate that the channel is either to provide a timebase value to the timer bus (71) for timebase channels (80, 81), or to receive the timebase value from the timer bus (71) for work and other channels (86). FIG. 15 illustrates examples of how timebase values (namely TB1-TB8) may be selectively provided during the different time slots of a timer bus (e.g. 71).
摘要翻译： 参见图 如图2，图13和图14所示，由时基选择信号（50）传送的标签值表示在定时器总线（71）上当前可用的时基。 在一个实施例中，每个通道（61,62,80,81和86）将时基选择信号（50）的标签值与存储在寄存器部分（264）中的用户编程的标签值进行比较。 如果所存储的标签值与在时基选择信号（50）上被驱动的标签值匹配，则确定匹配信号（263）以指示信道要么为时基提供时基值（71） 通道（80,81），或者从工作和其他通道（86）接收来自定时器总线（71）的时基值。 图。 图15示出了在定时器总线（例如71）的不同时隙期间如何选择性地提供时基值（即，TB1-TB8）的示例。
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公开(公告)号：US5042005A
公开(公告)日：1991-08-20
申请号：US234111
申请日：1988-08-19
IPC分类号： G06F1/14
CPC分类号： G06F1/14
摘要： A timer subsystem which provides a data processor servicing the timer subsystem with the ability to inhibit the match recognition logic of the timer subsystem while the processor is servicing the subsystem. The disclosed embodiment comprises a sixteen-channel timer subsystem with a dedicated service processor. The service processor, under control of the micro-coded programs executing thereon, is capable of disabling a match recognition latch in the timer channel currently being serviced. This feature provides the ability to prevent unwanted matches which occur while the service processor is updating the match register, for instance. Another feature of the timer subsystem is the inhibition of multiple matches to a single match register value by disabling the match recognition latch upon the occurrence of a match and re-enabling it only when the match register is written by the data processor.
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