Method of tooth detection
    1.
    发明授权
    Method of tooth detection 失效
    牙齿检测方法

    公开(公告)号:US5757875A

    公开(公告)日:1998-05-26

    申请号:US626161

    申请日:1996-04-01

    IPC分类号: G01D5/245 G06M3/00

    CPC分类号: G01D5/2457

    摘要: A method for identifying a principal tooth in a series of teeth extending along at least a portion of a periphery of a rotatable object includes the steps of rotating the rotatable object, setting a counter to a predetermined value, measuring a first tooth in the series of teeth to obtain a first measurement, adding a qualifying value to the measurement to obtain a qualification measurement, measuring a second tooth in the series of teeth to obtain a second measurement, comparing the second measurement to the qualification measurement, and identifying the second tooth as the principal tooth when the second measurement exceeds the qualification measurement.

    摘要翻译: 一种用于识别沿着可旋转物体的周边的至少一部分延伸的一系列齿中的主齿的方法包括以下步骤:使可旋转物体旋转,设定相对于预定值,测量该系列中的第一齿 以获得第一测量值,向测量值添加限定值以获得鉴定测量,测量所述一系列齿中的第二齿以获得第二测量,将所述第二测量与所述鉴定测量进行比较,以及将所述第二齿识别为 当第二次测量超过资格测量时的主齿。

    Electronic filtering device
    2.
    发明授权
    Electronic filtering device 失效
    电子过滤装置

    公开(公告)号:US5699009A

    公开(公告)日:1997-12-16

    申请号:US626160

    申请日:1996-04-01

    IPC分类号: H03K5/1252 H03K5/156 H03K5/00

    CPC分类号: H03K5/156 H03K5/1252

    摘要: A filtering device for filtering noise from an electronic signal having a plurality of defined periods includes an input terminal for receiving the electronic signal, a period divider for dividing each of the definable periods into an equal number of subdivisions, a filter creating a latching signal for a predetermined portion of the number of subdivisions, and a latch for receiving the latching signal from the filter and for maintaining the electronic signal in steady state for a predetermined portion of the number of subdivisions.

    摘要翻译: 用于从具有多个定义周期的电子信号滤波噪声的滤波装置包括用于接收电子信号的输入端,用于将每个可定义周期分成相等数目的分段的周期分配器,产生用于 子部分数量的预定部分,以及用于接收来自滤波器的锁存信号的锁存器,并且用于将电子信号保持在稳定状态以用于分组数量的预定部分。

    Queued serial peripheral interface having multiple queues for use in a
data processing system
    4.
    发明授权
    Queued serial peripheral interface having multiple queues for use in a data processing system 失效
    具有用于数据处理系统的多个队列的排队串行外设接口

    公开(公告)号:US5805922A

    公开(公告)日:1998-09-08

    申请号:US237437

    申请日:1994-05-02

    IPC分类号: G06F13/38 G06F13/00

    CPC分类号: G06F13/385

    摘要: Serial communication circuitry (10) having multiple queues (11-14) for use in a data processing system (95). Each queue (11-14) has multiple entries (52). Serial transfers from the multiple queues (11-14) are carried out under the control of global parameters (e.g. 205, 209), per-queue parameters (e.g. 211-212, 214-217), and per-entry parameters (e.g. 350-361). Each queue can be programmed to have a different set of per-queue parameters, and each entry within a queue can be programmed to have a different set of per-entry parameters. In addition, serial communication circuitry (10) can perform serial data transfers in response to the assertion of a trigger signal (30) from a source such as a timer (63) or a central processing unit (61). As a result, data transfers can be more precisely related to a particular timing signal or set of timing signals.

    摘要翻译: 具有用于数据处理系统(95)的多个队列(11-14)的串行通信电路(10)。 每个队列(11-14)具有多个条目(52)。 来自多个队列(11-14)的串行传输在全局参数(例如205,209),每队列参数(例如211-212,214-217)和每个入口参数(例如350 -361)。 每个队列可以被编程为具有不同的每队列参数集合,并且队列内的每个条目可被编程为具有不同的每个入口参数集合。 此外,串行通信电路(10)可以响应于来自诸如定时器(63)或中央处理单元(61)的源的触发信号(30)的断言来执行串行数据传输。 结果,数据传输可以更精确地与特定的定时信号或一组定时信号有关。

    Queued port data controller for microprocessor-based engine control applications
    5.
    发明授权
    Queued port data controller for microprocessor-based engine control applications 失效
    排队端口数据控制器,用于基于微处理器的发动机控制应用

    公开(公告)号:US06381532B1

    公开(公告)日:2002-04-30

    申请号:US09665094

    申请日:2000-09-20

    IPC分类号: G06F1310

    CPC分类号: G06F13/4059

    摘要: An engine control system comprising a host processor in operative communication with a data bus and a plurality of peripheral devices for communicating engine operating parameters. Each of the peripheral devices include a first and second transaction register for storing communication parameters for each of the corresponding plurality of peripheral devices. The control system also includes a queued port rate register (QRR) including a memory unit in operative communication with the plurality of peripheral devices for storing data for transmission to the plurality of peripheral devices in accordance with the first and second transaction registers. The system further includes a peripheral counter in operative communication with each of the plurality of peripheral devices. The peripheral counter is adapted to interrogate each of the plurality of peripheral devices and, when data has been written to one of the peripheral devices, update the peripheral device according to the memory unit data.

    摘要翻译: 一种发动机控制系统,包括与数据总线可操作地通信的主处理器和用于通信发动机操作参数的多个外围设备。 每个外围设备包括用于存储对应的多个外围设备中的每一个的通信参数的第一和第二事务寄存器。 控制系统还包括排队端口速率寄存器(QRR),其包括与多个外围设备进行操作通信的存储器单元,用于根据第一和第二事务寄存器存储用于传输到多个外围设备的数据。 该系统还包括与多个外围设备中的每一个操作通信的外围计数器。 周边计数器适于询问多个外围设备中的每一个,并且当数据已被写入外围设备之一时,根据存储器单元数据来更新外围设备。

    I/O multiplexer and pin controller with serial and parallel capabilities for microprocessor based engine control
    6.
    发明授权
    I/O multiplexer and pin controller with serial and parallel capabilities for microprocessor based engine control 失效
    I / O多路复用器和引脚控制器,具有串行和并行功能,用于基于微处理器的发动机控制

    公开(公告)号:US06978340B2

    公开(公告)日:2005-12-20

    申请号:US09774230

    申请日:2001-01-30

    IPC分类号: G06F13/42 G06F13/00

    CPC分类号: G06F13/4291

    摘要: A controller 12 has an I/O crossover switching network 14, an optional I/O network expansion 16, a plurality of serial I/O shifters 18, a clock generator 20 and I/O control logic 22. The I/O crossover-switching network 14 is also referred to as an I/O multiplexer. Serial data may be transferred between a serial I/O shifter and an external device by way of a dedicated serial data pin (SDATA) 24 or an optional alternate pathway 26 which uses one of a plurality of parallel pins 28. The optional alternate pathway 26 can be used when pins 28 are unavailable or to reduce the number of pins on the device 12. The controller is shown to communicate with an external device 30 also having parallel pins 32. While a single device 30 is shown, the external device 30 can be any number of a plurality of devices having serial and parallel signal pathways that is controlled by the microprocessor 10 of the present invention.

    摘要翻译: 控制器12具有I / O交叉交换网络14,可选的I / O网络扩展16,多个串行I / O移位器18,时钟发生器20和I / O控制逻辑22。 I / O交换交换网络14也称为I / O多路复用器。 串行数据可以通过专用串行数据引脚(SDATA)24或使用多个并行引脚28之一的可选的备用通路26在串行I / O移位器和外部设备之间传输。 当引脚28不可用或减少器件12上的引脚数时,可以使用可选的备选路径26。 控制器被示出为与具有并行销32的外部设备30通信。 虽然示出了单个设备30,但是外部设备30可以是具有由本发明的微处理器10控制的串行和并行信号路径的多个设备的任何数量。