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公开(公告)号：US5129078A
公开(公告)日：1992-07-07
申请号：US233786
申请日：1988-08-19
IPC分类号： G06F1/14 , G06F13/12 , G06F13/362 , G06F15/78
CPC分类号： G06F13/124
摘要： A system comprises a service processor and a plurality of operating units dependent on the service processor. The service processor responds to service requests from the operating units and services the operating units one at a time. A scheduler is responsible for assigning priority to the operating units and determining the order in which the service requests are handled. A register contains a value indicative of the operating unit currently being serviced and is under control of the scheduler. According to one aspect of the present invention the register is also under control of the service processor itself. Another register, under control of the service processor, is coupled to the scheduler to generate service requests thereto independent of the operating units. A memory addressable by the service processor stores data. The service processor is capable of generating addresses for the memory derived from the contents of the register indicative of the operating unit currently being serviced.
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公开(公告)号：US4952367A
公开(公告)日：1990-08-28
申请号：US234110
申请日：1988-08-19
IPC分类号： G06F1/14
CPC分类号： G06F1/14
摘要： A timer system comprises a plurality of timer channels serviced by a single service processor. Each of the timer channels is capable of both input (capture) and output (match) functions. The microprogrammed service processor is responsible for configuring each of the channels for their intended uses and for responding to service requests generated by the channels in response to the occurrence of timer events. Features of the timer channels include the ability to continuously execute capture functions without generating service requests, the ability to execute a single capture function and service request and protect the captured value from being overwritten until the service request has been responded to and the ability to combine match and capture functions in such a way as to place a time-out window on the capture event.
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公开(公告)号：US4942522A
公开(公告)日：1990-07-17
申请号：US234103
申请日：1988-08-19
摘要： A timer channel with multiple timer reference signals available to it which is capable of performing any input or output timer function with reference to any of the available reference signals. In addition, input timer functions may be related to the occurrence of output functions. For instance, the state of one timer reference may be captured automatically at a specified time referenced to another timer reference. Another feature of the invention provides for the creation of a time-out window for an input timer function through the use of a concurrent output function.
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4.发明授权Integrated circuit timer with multiple channels and dedicated service processor 失效多通道集成电路定时器和专用服务处理器
公开(公告)号：US4926319A
公开(公告)日：1990-05-15
申请号：US234104
申请日：1988-08-19
IPC分类号： G04G3/00 , G04G99/00 , G06F1/14 , G06F15/16 , G06F15/177
摘要： A timer system comprises multiple channels, each of which is capable of performing input and output timer functions referenced to any of a plurality of timer reference signals. In the preferred embodiment, sixteen independent channels are serviced by a processor dedicated to that purpose and each can perform capture and match functions referenced to either of two free-running counters.
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5.发明授权Integrated circuit timer with multiple channels and dedicated service processor 失效多通道集成电路定时器和专用服务处理器
公开(公告)号：US5204957A
公开(公告)日：1993-04-20
申请号：US954940
申请日：1992-09-30
摘要： A timer system comprises multiple channels, each of which is capable of performing input and output timer functions referenced to any of a plurality of timer reference signals. In the preferred embodiment, sixteen independent channels are serviced by a processor dedicated to that purpose and each can perform capture and match functions referenced to either of two free-running counters.
摘要翻译： 定时器系统包括多个通道，每个通道能够执行参考多个定时器参考信号中的任何一个的输入和输出定时器功能。 在优选实施例中，十六个独立信道由专用于该目的的处理器提供服务，并且每个可以执行参考两个自由运行计数器之一的捕获和匹配功能。
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6.发明授权Data and clock recovery system having a phase-locked-loop and which controls dynamic loop response of a data stream of unknown data format 失效数据和时钟恢复系统具有锁相环并且控制未知数据格式的数据流的动态环路响应
公开(公告)号：US4365210A
公开(公告)日：1982-12-21
申请号：US163380
申请日：1980-06-26
CPC分类号： H03L7/10
摘要： A data and clock recovery system for capturing and processing serial data of a type wherein data bits of an unknown format are interleaved with clock bits utilizes a phase lock loop capable of being operated in a capture mode or a tracking mode. The data stream is compared with an internally generated reference signal, and error pulses having widths proportional to the phase error are generated. In the capture mode, these error pulses are differentially processed to produce a control voltage which varies the frequency of a VCO which in turn alters the reference frequency. In the tracking mode, phase error pulses of fixed widths are processed only if the data bits occur in fixed windows. Differential amplifying means provide adjustable gain control of the error pulses. Means are provided for digitally controlling the loop's dynamic response when switching between the capture and tracking modes.
摘要翻译： 一种数据和时钟恢复系统，用于捕获和处理类型的串行数据，其中未知格式的数据位与时钟位交错，利用能够以捕获模式或跟踪模式操作的锁相环。 将数据流与内部产生的参考信号进行比较，产生具有与相位误差成比例的宽度的误差脉冲。 在捕获模式中，这些误差脉冲被差分处理以产生控制电压，该控制电压改变VCO的频率，从而改变参考频率。 在跟踪模式中，固定宽度的相位误差脉冲仅在数据位出现在固定窗口中时被处理。 差分放大装置提供误差脉冲的可调增益控制。 提供了在捕获和跟踪模式之间切换时数字控制环路的动态响应的手段。
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公开(公告)号：US4346452A
公开(公告)日：1982-08-24
申请号：US939743
申请日：1978-09-05
申请人： Stanley E. Groves
发明人： Stanley E. Groves
CPC分类号： H04L25/4904 , G06F13/385
摘要： A single-chip microcomputer comprises a CPU (1), a RAM (2), a ROM (3), a timer (4), serial I/O communication logic (5), and four I/O ports (11-14). The serial I/O communication logic is capable of handling serial communications in either the NRZ or Manchester (biphase) format. The result is more versatile and more reliable serial communications.
摘要翻译： 单片机包括CPU（1），RAM（2），ROM（3），定时器（4），串行I / O通信逻辑（5）和四个I / O端口（11-14 ）。 串行I / O通信逻辑能够处理NRZ或曼彻斯特（双相）格式的串行通信。 结果是更通用和更可靠的串行通信。
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8.发明授权Method and apparatus for selectively delaying an interrupt of a coprocessor 失效用于选择性地延迟协处理器的中断的方法和装置
公开(公告)号：US4758950A
公开(公告)日：1988-07-19
申请号：US113343
申请日：1987-04-13
CPC分类号： G06F9/3881 , G06F9/3861
摘要： A system for interfacing a Processor to a Coprocessor using standard bus cycles. The Processor, upon encountering in its instruction stream an instruction having a particular Operation word format, will transfer a Command word following the Operation word to a particular Coprocessor designated by a Coprocessor Identity field in the Operation word. Upon decoding the Command word, the Coprocessor will respond with any of a set of response primitives which define functions which the Coprocessor requires to Processor to perform in support of the Command by the Coprocessor. The interface provides for all functions which the Coprocessor may require, including selective vectoring to appropriate exception handlers.
摘要翻译： 使用标准总线周期将处理器与协处理器进行接口的系统。 处理器在其指令流中遇到具有特定操作字格式的指令时，将将操作字后的命令字传送到由操作字中的协处理器标识字段指定的特定协处理器。 在解码命令字后，协处理器将响应一组响应原语中的任何一个，这些响应原语定义了协处理器要求处理器在协处理器支持命令时执行的功能。 该接口提供了协处理器可能需要的所有功能，包括向适当的异常处理程序选择性向量化。
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9.发明授权
公开(公告)号：US4361876A
公开(公告)日：1982-11-30
申请号：US939742
申请日：1978-09-05
申请人： Stanley E. Groves
发明人： Stanley E. Groves
IPC分类号： G06F13/00 , G06F13/12 , G06F13/38 , G06F15/16 , G06F15/78 , H03M5/12 , H04L7/00 , H04L25/49 , G06F3/00 , G06F7/00
CPC分类号： H04L25/4904 , G06F15/161
摘要： A single-chip microcomputer includes a CPU (1), a RAM (2), a ROM (3), a timer (4), serial I/O communication logic (5), and four I/O ports (11-14). The serial I/O communication logic includes a control and status register (46), one bit (WU) of which may be utilized, when the microcomputer is connected in a distributed processing system having a shared serial communication line, to indicate that the CPU wishes to ignore a message not of interest to it. When the serial communication line again becomes free, the WU control bit is reset, enabling the CPU to intercept a new message of interest.
摘要翻译： 单片机包括CPU（1），RAM（2），ROM（3），定时器（4），串行I / O通信逻辑（5）和四个I / O端口（11-14 ）。 当微型计算机连接在具有共享串行通信线路的分布式处理系统中时，串行I / O通信逻辑包括控制和状态寄存器（46），其中可以使用一位（WU），以指示CPU 希望忽略一个不感兴趣的信息。 当串行通信线路再次变为空闲时，WU控制位复位，使CPU能够拦截新的感兴趣的消息。
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公开(公告)号：US4317053A
公开(公告)日：1982-02-23
申请号：US100785
申请日：1979-12-05
申请人： Pern Shaw , Stanley E. Groves
发明人： Pern Shaw , Stanley E. Groves
CPC分类号： H03K5/135
摘要： In a high speed synchronizing circuit, the rising edge of an asynchronous input signal is used to set an input RS flip-flop. First and second latch registers monitor the input RS flip-flop. Each latch register generates a reset signal before a change in the logic level of the system clock for resetting the input RS flip-flop. The reset pulses are very narrow which enables the RS flip-flop to be quickly conditioned to receive the next asynchronous signal.
摘要翻译： 在高速同步电路中，异步输入信号的上升沿用于设置输入RS触发器。 第一和第二锁存寄存器监视输入RS触发器。 在用于复位输入RS触发器的系统时钟的逻辑电平变化之前，每个锁存寄存器产生一个复位信号。 复位脉冲非常窄，这使得RS触发器能够被快速调节以接收下一个异步信号。
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