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1.发明授权Multi-step deposition of a spacer material for reducing void formation in a dielectric material of a contact level of a semiconductor device 有权用于减少半导体器件的接触电平的电介质材料中的空隙形成的间隔材料的多步沉积公开(公告)号：US08987103B2
公开(公告)日：2015-03-24
申请号：US12776674
申请日：2010-05-10
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/768
CPC分类号： H01L21/823468 , H01L21/76837 , H01L21/76895 , H01L21/823425
摘要： In advanced semiconductor devices, spacer elements may be formed on the basis of a multi-station deposition technique, wherein a certain degree of variability of the various sub-layers of the spacer materials, such as a different thickness, may be applied in order to enhance etch conditions during the subsequent anisotropic etch process. Consequently, spacer elements of improved shape may result in superior deposition conditions when using a stress-inducing dielectric material. Consequently, yield losses due to contact failures in densely packed device areas, such as static RAM areas, may be reduced.
摘要翻译： 在先进的半导体器件中，可以基于多工段沉积技术形成间隔元件，其中可以应用间隔材料的各个子层的一定程度的变化性，例如不同的厚度，以便 在随后的各向异性蚀刻工艺期间增强蚀刻条件。 因此，当使用应力诱导介电材料时，改进形状的间隔元件可能导致优异的沉积条件。 因此，由于紧密封装的设备区域（例如静态RAM区域）中的接触故障导致的屈服损失可能会降低。
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2.发明授权Enhanced cap layer integrity in a high-K metal gate stack by using a hard mask for offset spacer patterning 有权通过使用用于偏移间隔物图案化的硬掩模，在高K金属栅极堆叠中增强了覆盖层的完整性公开(公告)号：US07981740B2
公开(公告)日：2011-07-19
申请号：US12821583
申请日：2010-06-23
申请人： Markus Lenski , Kerstin Ruttloff , Martin Mazur , Frank Seliger , Ralf Otterbach
发明人： Markus Lenski , Kerstin Ruttloff , Martin Mazur , Frank Seliger , Ralf Otterbach
IPC分类号： H01L21/8238 , H01L21/336
CPC分类号： H01L21/823864 , H01L21/823807 , H01L29/7843
摘要： When forming transistor elements on the basis of sophisticated high-k metal gate structures, the efficiency of a replacement gate approach may be enhanced by more efficiently adjusting the gate height of transistors of different conductivity type when the dielectric cap layers of transistors may have experienced a different process history and may thus require a subsequent adaptation of the final cap layer thickness in one type of the transistors. For this purpose, a hard mask material may be used during a process sequence for forming offset spacer elements in one gate electrode structure while covering another gate electrode structure.
摘要翻译： 当在复杂的高k金属栅极结构的基础上形成晶体管元件时，可以通过更有效地调节不同导电类型的晶体管的栅极高度来增强置换栅极方法的效率，当晶体管的介质盖层可能经历了 因此可能需要在一种类型的晶体管中随后适应最终的盖层厚度。 为此，可以在用于在一个栅电极结构中形成偏移间隔元件同时覆盖另一栅电极结构的处理顺序期间使用硬掩模材料。
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3.发明申请ENHANCED CAP LAYER INTEGRITY IN A HIGH-K METAL GATE STACK BY USING A HARD MASK FOR OFFSET SPACER PATTERNING 有权通过使用硬掩模进行偏角平铺图案，在高K金属盖板上增强了盖层的整体性公开(公告)号：US20100330757A1
公开(公告)日：2010-12-30
申请号：US12821583
申请日：2010-06-23
申请人： Markus Lenski , Kerstin Ruttloff , Martin Mazur , Frank Seliger , Ralf Otterbach
发明人： Markus Lenski , Kerstin Ruttloff , Martin Mazur , Frank Seliger , Ralf Otterbach
IPC分类号： H01L21/8238 , H01L21/8234
CPC分类号： H01L21/823864 , H01L21/823807 , H01L29/7843
摘要： When forming transistor elements on the basis of sophisticated high-k metal gate structures, the efficiency of a replacement gate approach may be enhanced by more efficiently adjusting the gate height of transistors of different conductivity type when the dielectric cap layers of transistors may have experienced a different process history and may thus require a subsequent adaptation of the final cap layer thickness in one type of the transistors. For this purpose, a hard mask material may be used during a process sequence for forming offset spacer elements in one gate electrode structure while covering another gate electrode structure.
摘要翻译： 当在复杂的高k金属栅极结构的基础上形成晶体管元件时，可以通过更有效地调节不同导电类型的晶体管的栅极高度来增强置换栅极方法的效率，当晶体管的介质盖层可能经历了 因此可能需要在一种类型的晶体管中随后适应最终的盖层厚度。 为此，可以在用于在一个栅电极结构中形成偏移间隔元件同时覆盖另一栅电极结构的处理顺序期间使用硬掩模材料。
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4.发明申请DOPANT PROFILE TUNING FOR MOS DEVICES BY ADAPTING A SPACER WIDTH PRIOR TO IMPLANTATION 有权通过在植入前适应间隔宽度，用于MOS器件的眩光轮廓调谐公开(公告)号：US20090108295A1
公开(公告)日：2009-04-30
申请号：US12108992
申请日：2008-04-24
申请人： Anthony Mowry , Markus Lenski , Guido Koerner , Ralf Otterbach
发明人： Anthony Mowry , Markus Lenski , Guido Koerner , Ralf Otterbach
IPC分类号： H01L29/78 , H01L21/225
CPC分类号： H01L21/823864 , H01L21/823412 , H01L21/823418 , H01L21/823468 , H01L21/823807 , H01L21/823814 , H01L29/6653 , H01L29/6656 , H01L29/6659
摘要： By selectively modifying the spacer width, for instance, by reducing the spacer width on the basis of implantation masks, an individual adaptation of dopant profiles may be achieved without unduly contributing to the overall process complexity. For example, in sophisticated integrated circuits, the performance of transistors of the same or different conductivity type may be individually adjusted by providing different sidewall spacer widths on the basis of an appropriate masking regime.
摘要翻译： 通过例如通过基于注入掩模减小间隔物宽度来选择性地修改间隔物宽度，可以实现单独的掺杂剂轮廓的适应性，而不会不利地导致整个工艺复杂性。 例如，在复杂的集成电路中，相同或不同导电类型的晶体管的性能可以通过基于适当的掩蔽状态提供不同的侧壁间隔物宽度来单独调节。
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5.发明申请DOPANT PROFILE TUNING FOR MOS DEVICES BY ADAPTING A SPACER WIDTH PRIOR TO IMPLANTATION 有权通过在植入前适应间隔宽度，用于MOS器件的眩光轮廓调谐公开(公告)号：US20110230039A1
公开(公告)日：2011-09-22
申请号：US13152350
申请日：2011-06-03
申请人： Anthony Mowry , Markus Lenski , Guido Koerner , Ralf Otterbach
发明人： Anthony Mowry , Markus Lenski , Guido Koerner , Ralf Otterbach
IPC分类号： H01L21/265
CPC分类号： H01L21/823864 , H01L21/823412 , H01L21/823418 , H01L21/823468 , H01L21/823807 , H01L21/823814 , H01L29/6653 , H01L29/6656 , H01L29/6659
摘要： By selectively modifying the spacer width, for instance, by reducing the spacer width on the basis of implantation masks, an individual adaptation of dopant profiles may be achieved without unduly contributing to the overall process complexity. For example, in sophisticated integrated circuits, the performance of transistors of the same or different conductivity type may be individually adjusted by providing different sidewall spacer widths on the basis of an appropriate masking regime.
摘要翻译： 通过例如通过基于注入掩模减小间隔物宽度来选择性地修改间隔物宽度，可以实现单独的掺杂剂轮廓的适应性，而不会不利地导致整个工艺复杂性。 例如，在复杂的集成电路中，相同或不同导电类型的晶体管的性能可以通过基于适当的掩蔽状态提供不同的侧壁间隔物宽度来单独调节。
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6.发明授权Dopant profile tuning for MOS devices by adapting a spacer width prior to implantation 有权通过在植入前适应间隔物宽度，MOS器件的掺杂分布调谐公开(公告)号：US08507351B2
公开(公告)日：2013-08-13
申请号：US13152350
申请日：2011-06-03
申请人： Anthony Mowry , Markus Lenski , Guido Koerner , Ralf Otterbach
发明人： Anthony Mowry , Markus Lenski , Guido Koerner , Ralf Otterbach
IPC分类号： H01L21/336 , H01L21/8238
CPC分类号： H01L21/823864 , H01L21/823412 , H01L21/823418 , H01L21/823468 , H01L21/823807 , H01L21/823814 , H01L29/6653 , H01L29/6656 , H01L29/6659
摘要： By selectively modifying the spacer width, for instance, by reducing the spacer width on the basis of implantation masks, an individual adaptation of dopant profiles may be achieved without unduly contributing to the overall process complexity. For example, in sophisticated integrated circuits, the performance of transistors of the same or different conductivity type may be individually adjusted by providing different sidewall spacer widths on the basis of an appropriate masking regime.
摘要翻译： 通过例如通过基于注入掩模减小间隔物宽度来选择性地修改间隔物宽度，可以实现单独的掺杂剂轮廓的适应性，而不会不利地导致整个工艺复杂性。 例如，在复杂的集成电路中，相同或不同导电类型的晶体管的性能可以通过基于适当的掩蔽状态提供不同的侧壁间隔物宽度来单独调节。
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7.发明授权Dopant profile tuning for MOS devices by adapting a spacer width prior to implantation 有权通过在植入前适应间隔物宽度，MOS器件的掺杂分布调谐公开(公告)号：US07977179B2
公开(公告)日：2011-07-12
申请号：US12108992
申请日：2008-04-24
申请人： Anthony Mowry , Markus Lenski , Guido Koerner , Ralf Otterbach
发明人： Anthony Mowry , Markus Lenski , Guido Koerner , Ralf Otterbach
IPC分类号： H01L21/8238 , H01L21/336
CPC分类号： H01L21/823864 , H01L21/823412 , H01L21/823418 , H01L21/823468 , H01L21/823807 , H01L21/823814 , H01L29/6653 , H01L29/6656 , H01L29/6659
摘要： By selectively modifying the spacer width, for instance, by reducing the spacer width on the basis of implantation masks, an individual adaptation of dopant profiles may be achieved without unduly contributing to the overall process complexity. For example, in sophisticated integrated circuits, the performance of transistors of the same or different conductivity type may be individually adjusted by providing different sidewall spacer widths on the basis of an appropriate masking regime.
摘要翻译： 通过例如通过基于注入掩模减小间隔物宽度来选择性地修改间隔物宽度，可以实现单独的掺杂剂轮廓的适应性，而不会不利地导致整个工艺复杂性。 例如，在复杂的集成电路中，相同或不同导电类型的晶体管的性能可以通过基于适当的掩蔽状态提供不同的侧壁间隔物宽度来单独调节。
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公开(公告)号：US20130037866A1
公开(公告)日：2013-02-14
申请号：US13209061
申请日：2011-08-12
申请人： Hans-Jürgen Thees , Roman Boschke , Ralf Otterbach
发明人： Hans-Jürgen Thees , Roman Boschke , Ralf Otterbach
CPC分类号： H01L29/66659 , H01L21/823468 , H01L29/6653 , H01L29/6656
摘要： A method for forming a semiconductor device includes providing a substrate and depositing a gate stack having a side periphery on the substrate. A first liner dielectric layer is deposited on the substrate and the gate stack. A first spacer dielectric layer is deposited on the first liner dielectric layer. The first spacer dielectric layer is selectively etched such that the first spacer dielectric layer remains adjacent at least a portion of the side periphery of the gate stack. A first resist mask is disposed on a first portion of the first spacer dielectric layer such that the first portion of the first spacer dielectric layer is protected by the resist mask and a second portion of the first spacer dielectric layer is not protected by the resist mask. The first spacer dielectric layer is etched such that the second portion is removed and the first portion remains.
摘要翻译： 一种用于形成半导体器件的方法包括提供衬底并在衬底上沉积具有侧边缘的栅极堆叠。 第一衬里介电层沉积在衬底和栅极叠层上。 第一间隔电介质层沉积在第一衬垫电介质层上。 选择性地蚀刻第一间隔电介质层，使得第一间隔物介质层保持邻近栅堆叠的侧边缘的至少一部分。 第一抗蚀剂掩模设置在第一间隔电介质层的第一部分上，使得第一间隔电介质层的第一部分被抗蚀剂掩模保护，并且第一间隔物介电层的第二部分不被抗蚀剂掩模保护 。 蚀刻第一间隔电介质层，使得第二部分被去除并且第一部分保留。
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