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1.发明授权Multi-step deposition of a spacer material for reducing void formation in a dielectric material of a contact level of a semiconductor device 有权用于减少半导体器件的接触电平的电介质材料中的空隙形成的间隔材料的多步沉积公开(公告)号：US08987103B2
公开(公告)日：2015-03-24
申请号：US12776674
申请日：2010-05-10
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/768
CPC分类号： H01L21/823468 , H01L21/76837 , H01L21/76895 , H01L21/823425
摘要： In advanced semiconductor devices, spacer elements may be formed on the basis of a multi-station deposition technique, wherein a certain degree of variability of the various sub-layers of the spacer materials, such as a different thickness, may be applied in order to enhance etch conditions during the subsequent anisotropic etch process. Consequently, spacer elements of improved shape may result in superior deposition conditions when using a stress-inducing dielectric material. Consequently, yield losses due to contact failures in densely packed device areas, such as static RAM areas, may be reduced.
摘要翻译： 在先进的半导体器件中，可以基于多工段沉积技术形成间隔元件，其中可以应用间隔材料的各个子层的一定程度的变化性，例如不同的厚度，以便 在随后的各向异性蚀刻工艺期间增强蚀刻条件。 因此，当使用应力诱导介电材料时，改进形状的间隔元件可能导致优异的沉积条件。 因此，由于紧密封装的设备区域（例如静态RAM区域）中的接触故障导致的屈服损失可能会降低。
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2.发明申请ENHANCED ADHESION OF PECVD CARBON ON DIELECTRIC MATERIALS BY PROVIDING AN ADHESION INTERFACE 有权通过提供粘合界面增强PECVD碳对电介质材料的粘附公开(公告)号：US20110104866A1
公开(公告)日：2011-05-05
申请号：US12898822
申请日：2010-10-06
申请人： Hartmut Ruelke , Volker Jaschke
发明人： Hartmut Ruelke , Volker Jaschke
IPC分类号： H01L21/764 , H01L21/467
CPC分类号： H01L21/31144 , H01L21/02115 , H01L21/02164 , H01L21/02274 , H01L21/02304 , H01L21/02315 , H01L21/3105 , H01L21/3146 , H01L21/32139
摘要： Amorphous carbon material may be deposited with superior adhesion on dielectric materials, such as TEOS based silicon oxide materials, in complex semiconductor devices by applying a plasma treatment, such as an argon treatment and/or forming a thin adhesion layer based on silicon dioxide, carbon-doped silicon dioxide, prior to depositing the carbon material. Consequently, the hard mask concept based on amorphous carbon may be applied with an increased degree of flexibility, since a superior adhesion may allow a higher degree of flexibility in selecting appropriate deposition parameters for the carbon material.
摘要翻译： 非晶碳材料可以通过施加诸如氩处理的等离子体处理和/或形成基于二氧化硅，碳的薄粘合层，在复杂的半导体器件中沉积具有优异的电介质材料（例如基于TEOS的氧化硅材料）的附着力 在沉积碳材料之前，将二氧化硅掺杂。 因此，基于无定形碳的硬掩模概念可以被应用于增加的柔性程度，因为优异的粘附性可以允许在为碳材料选择合适的沉积参数时具有更高的灵活性。
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3.发明申请REDUCING CRITICAL DIMENSIONS OF VIAS AND CONTACTS ABOVE THE DEVICE LEVEL OF SEMICONDUCTOR DEVICES 审中-公开降低半导体器件的器件级VIAS和联系人的关键尺寸公开(公告)号：US20100055902A1
公开(公告)日：2010-03-04
申请号：US12506678
申请日：2009-07-21
申请人： Kai Frohberg , Sven Mueller , Tino Hertzsch , Volker Jaschke
发明人： Kai Frohberg , Sven Mueller , Tino Hertzsch , Volker Jaschke
IPC分类号： H01L21/768 , H01L21/302
CPC分类号： H01L21/76816 , H01L21/0337 , H01L21/31144
摘要： Contact elements may be formed on the basis of a mask layer having openings, the width of which may be reduced by etching or deposition, thereby extending the process margins for a given lithography technique. Consequently, yield losses caused by short circuits in the contact level of sophisticated semiconductor devices may be reduced.
摘要翻译： 接触元件可以基于具有开口的掩模层形成，其宽度可以通过蚀刻或沉积来减小，从而延长给定光刻技术的工艺边缘。 因此，可能降低由复杂的半导体器件的接触电平的短路导致的屈服损失。
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4.发明授权Stress engineering in a contact level of semiconductor devices by stressed conductive layers and an isolation spacer 有权通过应力导电层和隔离间隔器在半导体器件的接触电平中进行应力工程公开(公告)号：US08338284B2
公开(公告)日：2012-12-25
申请号：US12891301
申请日：2010-09-27
申请人： Kai Frohberg , Hartmut Ruelke , Volker Jaschke , Joerg Hohage , Frank Seliger
发明人： Kai Frohberg , Hartmut Ruelke , Volker Jaschke , Joerg Hohage , Frank Seliger
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L21/76834 , H01L21/76801 , H01L21/76831 , H01L21/76832 , H01L21/76841 , H01L21/76897 , H01L29/7845
摘要： In sophisticated semiconductor devices, strain-inducing materials having a reduced dielectric strength or having certain conductivity, such as metal nitride and the like, may be used in the contact level in order to enhance performance of circuit elements, such as field effect transistors. For this purpose, a strain-inducing material may be efficiently encapsulated on the basis of a dielectric layer stack that may be patterned prior to forming the actual interlayer dielectric material in order to mask sidewall surface areas on the basis of spacer elements.
摘要翻译： 在复杂的半导体器件中，可以在接触电平中使用具有降低的介电强度或具有一定导电性的应变诱导材料，例如金属氮化物等，以增强诸如场效应晶体管的电路元件的性能。 为此目的，应变诱导材料可以在形成实际的层间电介质材料之前被图案化的介电层堆叠被有效地封装，以便基于间隔元件掩盖侧壁表面区域。
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5.发明申请STRESS ENGINEERING IN A CONTACT LEVEL OF SEMICONDUCTOR DEVICES BY STRESSED CONDUCTIVE LAYERS AND AN ISOLATION SPACER 有权通过受阻导电层和隔离间隔的接触层半导体器件的应力工程公开(公告)号：US20110073959A1
公开(公告)日：2011-03-31
申请号：US12891301
申请日：2010-09-27
申请人： Kai Frohberg , Hartmut Ruelke , Volker Jaschke , Joerg Hohage , Frank Seliger
发明人： Kai Frohberg , Hartmut Ruelke , Volker Jaschke , Joerg Hohage , Frank Seliger
CPC分类号： H01L21/76834 , H01L21/76801 , H01L21/76831 , H01L21/76832 , H01L21/76841 , H01L21/76897 , H01L29/7845
摘要： In sophisticated semiconductor devices, strain-inducing materials having a reduced dielectric strength or having certain conductivity, such as metal nitride and the like, may be used in the contact level in order to enhance performance of circuit elements, such as field effect transistors. For this purpose, a strain-inducing material may be efficiently encapsulated on the basis of a dielectric layer stack that may be patterned prior to forming the actual interlayer dielectric material in order to mask sidewall surface areas on the basis of spacer elements.
摘要翻译： 在复杂的半导体器件中，可以在接触电平中使用具有降低的介电强度或具有一定导电性的应变诱导材料，例如金属氮化物等，以增强诸如场效应晶体管的电路元件的性能。 为此目的，应变诱导材料可以在形成实际的层间电介质材料之前被图案化的介电层堆叠被有效地封装，以便基于间隔元件掩盖侧壁表面区域。
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6.发明授权Enhanced adhesion of PECVD carbon on dielectric materials by providing an adhesion interface 有权通过提供粘合界面来增强PECVD碳对介电材料的粘附公开(公告)号：US08415257B2
公开(公告)日：2013-04-09
申请号：US12898822
申请日：2010-10-06
申请人： Hartmut Ruelke , Volker Jaschke
发明人： Hartmut Ruelke , Volker Jaschke
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/31144 , H01L21/02115 , H01L21/02164 , H01L21/02274 , H01L21/02304 , H01L21/02315 , H01L21/3105 , H01L21/3146 , H01L21/32139
摘要： Amorphous carbon material may be deposited with superior adhesion on dielectric materials, such as TEOS based silicon oxide materials, in complex semiconductor devices by applying a plasma treatment, such as an argon treatment and/or forming a thin adhesion layer based on silicon dioxide, carbon-doped silicon dioxide, prior to depositing the carbon material. Consequently, the hard mask concept based on amorphous carbon may be applied with an increased degree of flexibility, since a superior adhesion may allow a higher degree of flexibility in selecting appropriate deposition parameters for the carbon material.
摘要翻译： 非晶碳材料可以通过施加诸如氩处理的等离子体处理和/或形成基于二氧化硅，碳的薄粘合层，在复杂的半导体器件中沉积具有优异的电介质材料（例如基于TEOS的氧化硅材料）的附着力 在沉积碳材料之前，将二氧化硅掺杂。 因此，基于无定形碳的硬掩模概念可以被应用于增加的柔性程度，因为优异的粘附性可以允许在为碳材料选择合适的沉积参数时具有更高的灵活性。
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7.发明申请Oxide Deposition by Using a Double Liner Approach for Reducing Pattern Density Dependence in Sophisticated Semiconductor Devices 有权通过使用双层衬底方法来降低精密半导体器件中的图案密度依赖性的氧化物沉积公开(公告)号：US20120049296A1
公开(公告)日：2012-03-01
申请号：US13183549
申请日：2011-07-15
IPC分类号： H01L29/772 , H01L21/336 , H01L21/314
CPC分类号： H01L21/823807 , H01L21/02126 , H01L21/02164 , H01L21/022 , H01L21/02274 , H01L21/823814 , H01L21/823864 , H01L21/823871 , H01L29/6656 , H01L29/66636 , H01L29/7848
摘要： A silicon dioxide material may be provided in sophisticated semiconductor devices in the form of a double liner including an undoped silicon dioxide material in combination with a high density plasma silicon dioxide, thereby providing reduced dependency on pattern density. In some illustrative embodiments, the silicon dioxide double liner may be used as a spacer material and as a hard mask material in process strategies for incorporating a strain-inducing semiconductor material.
摘要翻译： 可以在复合半导体器件中提供二氧化硅材料，其形式为双层衬垫，其包括与高密度等离子体二氧化硅组合的未掺杂二氧化硅材料，从而降低对图案密度的依赖性。 在一些说明性实施例中，二氧化硅双层衬垫可以用作间隔材料，并且可用作掺入应变诱导半导体材料的工艺策略中的硬掩模材料。
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8.发明申请MULTI-STEP DEPOSITION OF A SPACER MATERIAL FOR REDUCING VOID FORMATION IN A DIELECTRIC MATERIAL OF A CONTACT LEVEL OF A SEMICONDUCTOR DEVICE 有权用于减少半导体器件的接触层的介电材料中的失速形成的间隔材料的多步沉积公开(公告)号：US20100289083A1
公开(公告)日：2010-11-18
申请号：US12776674
申请日：2010-05-10
申请人： Markus Lenski , Kerstin Ruttloff , Volker Jaschke , Frank Seliger
发明人： Markus Lenski , Kerstin Ruttloff , Volker Jaschke , Frank Seliger
IPC分类号： H01L27/088 , H01L21/336
CPC分类号： H01L21/823468 , H01L21/76837 , H01L21/76895 , H01L21/823425
摘要： In advanced semiconductor devices, spacer elements may be formed on the basis of a multi-station deposition technique, wherein a certain degree of variability of the various sub-layers of the spacer materials, such as a different thickness, may be applied in order to enhance etch conditions during the subsequent anisotropic etch process. Consequently, spacer elements of improved shape may result in superior deposition conditions when using a stress-inducing dielectric material. Consequently, yield losses due to contact failures in densely packed device areas, such as static RAM areas, may be reduced.
摘要翻译： 在先进的半导体器件中，可以基于多工段沉积技术形成间隔元件，其中可以应用间隔材料的各个子层的一定程度的变化性，例如不同的厚度，以便 在随后的各向异性蚀刻工艺期间增强蚀刻条件。 因此，当使用应力诱导介电材料时，改进形状的间隔元件可能导致优异的沉积条件。 因此，由于紧密封装的设备区域（例如静态RAM区域）中的接触故障导致的屈服损失可能会降低。
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9.发明授权Oxide deposition by using a double liner approach for reducing pattern density dependence in sophisticated semiconductor devices 有权通过使用双层衬垫方法来降低复杂半导体器件中的图案密度依赖性的氧化物沉积公开(公告)号：US08772843B2
公开(公告)日：2014-07-08
申请号：US13183549
申请日：2011-07-15
IPC分类号： H01L29/76 , H01L21/02 , H01L21/31 , H01L21/461 , H01L21/8238 , H01L29/66 , H01L29/78
CPC分类号： H01L21/823807 , H01L21/02126 , H01L21/02164 , H01L21/022 , H01L21/02274 , H01L21/823814 , H01L21/823864 , H01L21/823871 , H01L29/6656 , H01L29/66636 , H01L29/7848
摘要： A silicon dioxide material may be provided in sophisticated semiconductor devices in the form of a double liner including an undoped silicon dioxide material in combination with a high density plasma silicon dioxide, thereby providing reduced dependency on pattern density. In some illustrative embodiments, the silicon dioxide double liner may be used as a spacer material and as a hard mask material in process strategies for incorporating a strain-inducing semiconductor material.
摘要翻译： 可以在复合半导体器件中提供二氧化硅材料，其形式为双层衬垫，其包括与高密度等离子体二氧化硅组合的未掺杂二氧化硅材料，从而降低对图案密度的依赖性。 在一些说明性实施例中，二氧化硅双层衬垫可以用作间隔材料，并且可用作掺入应变诱导半导体材料的工艺策略中的硬掩模材料。
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