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公开(公告)号：US06792175B2
公开(公告)日：2004-09-14
申请号：US09726640
申请日：2000-11-30
IPC分类号： G02B635
CPC分类号： G02F1/31 , G02B6/3556 , G02B6/3594 , G02F1/13471 , G02F2203/07
摘要： A free space all-optical crossbar switches light from a plurality of sources onto a plurality of receivers, in any arbitrary permutation or combination (including one-to-one and many-to-one permutations). The sources and receivers may, for example, be single mode optical fibers. The polarization of the light from each source is controlled by a series of polarization control devices associated with the source so as to obtain desired angular deflections through a series of polarization-dependent angular deflectors in a first deflection unit. A lens may then direct the light from each source towards its desired receiver. An optional second deflection unit containing polarization control devices associated with individual receivers redirects the light so that it is incident normally on the receivers, an advantage if the receivers are single mode optical fibers. Alternative embodiments are described to reduce the number of optical components and to provide uninterrupted high speed data flow.
摘要翻译： 自由空间全光交叉开关将光从多个源切换到多个接收器，以任何任意的排列或组合（包括一对一和多对一排列）。 源和接收器可以例如是单模光纤。 来自每个源的光的偏振由与源相关联的一系列偏振控制装置控制，以便通过第一偏转单元中的一系列偏振相关角偏转器获得期望的角偏转。 然后，透镜可以将来自每个源的光引导到其期望的接收器。 包含与单个接收器相关联的偏振控制装置的可选的第二偏转单元重定向光，使得其正常地入射在接收器上，如果接收器是单模光纤，则具有优点。 描述了替代实施例以减少光学部件的数量并提供不间断的高速数据流。
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公开(公告)号：US06332050B1
公开(公告)日：2001-12-18
申请号：US09543617
申请日：2000-04-05
IPC分类号： G02B628
CPC分类号： G02B6/29344 , G02B6/10 , G02B6/2817 , G02B6/2848 , G02B6/43 , H04J14/02 , H04J14/04
摘要： Optical slab waveguides are used as high-speed, high-capacity interconnects for parallel or other devices. Optical slab interconnects can connect to many more elements than can conventional electrical or fiber optic buses. A multiplexing scheme called “mode division multiplexing” greatly increases the number of independent channels that a single slab can support. Optical slab waveguides have a potential capacity of over one million independent channels, each channel operating at 1 GHz in a single physical medium, with each channel capable of receiving input from over 1000 ports and sustaining a load of over 1000.
摘要翻译： 光学平板波导用作并行或其他设备的高速，大容量互连。 光学平板互连可以连接到比常规电气或光纤总线更多的元件。 称为“模式分复用”的复用方案大大增加了单个板可以支持的独立信道的数量。 光学平板波导具有超过一百万个独立通道的潜在容量，每个通道在单个物理介质中以1 GHz工作，每个通道能够接收来自1000个端口的输入，并承受1000次以上的负载。
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公开(公告)号：US08862854B2
公开(公告)日：2014-10-14
申请号：US12310217
申请日：2007-08-20
IPC分类号： G06F12/10 , H03K19/177 , H03K19/173
CPC分类号： H03K19/17776 , H03K19/1732 , H03K19/17744 , H03K19/17752 , H03K19/17756
摘要： The invention relates to hardware decoders that efficiently expand a small number of input bits to a large number of output bits, while providing considerable flexibility in selecting the output instances. One main area of application of the invention is in pin-limited environments, such as field programmable gates array (FPGA) used with dynamic reconfiguration. The invention includes a mapping unit that is a circuit, possibly in combination with a reconfigurable memory device. The circuit has as input a z-bit source word having a value at each bit position and it outputs an n-bit output word, where n>z, where the value of each bit position of the n-bit output word is based upon the value of a pre-selected hardwired one of the bit positions in the x-bit word, where the said pre-selected hardwired bit positions is selected by a selector address. The invention may include a second reconfigurable memory device that outputs the z-bit source word, based upon an x-bit source address input to the second memory device, where x
摘要翻译： 本发明涉及将少量输入位有效地扩展到大量输出位的硬件解码器，同时在选择输出实例方面提供相当大的灵活性。 本发明的一个主要应用领域是引脚限制环境，例如与动态重新配置一起使用的现场可编程门阵列（FPGA）。 本发明包括映射单元，其是可能与可重新配置的存储器件组合的电路。 电路具有作为输入的z位源字，其在每个位位置具有值，并且其输出n位输出字，其中n> z，其中n位输出字的每个位位置的值基于 通过选择器地址选择所述预选硬连线位位置的x位字中的预选硬连线位之一的值。 本发明可以包括基于输入到第二存储器设备的x位源地址输出z位源字的第二可重构存储器件，其中x
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公开(公告)号：US20100180098A1
公开(公告)日：2010-07-15
申请号：US12310217
申请日：2007-08-20
IPC分类号： G06F12/10
CPC分类号： H03K19/17776 , H03K19/1732 , H03K19/17744 , H03K19/17752 , H03K19/17756
摘要： The invention relates to hardware decoders that efficiently expand a small number of input bits to a large number of output bits, while providing considerable flexibility in selecting the output instances. One main area of application of the invention is in pin-limited environments, such as field programmable gates array (FPGA) used with dynamic reconfiguration. The invention includes a mapping unit that is a circuit, possibly in combination with a reconfigurable memory device. The circuit has as input a z-bit source word having a value at each bit position and it outputs an n-bit output word, where n>z, where the value of each bit position of the n-bit output word is based upon the value of a pre-selected hardwired one of the bit positions in the x-bit word, where the said pre-selected hardwired bit positions is selected by a selector address. The invention may include a second reconfigurable memory device that outputs the z-bit source word, based upon an x-bit source address input to the second memory device, where x
摘要翻译： 本发明涉及将少量输入位有效地扩展到大量输出位的硬件解码器，同时在选择输出实例方面提供相当大的灵活性。 本发明的一个主要应用领域是引脚限制环境，例如与动态重新配置一起使用的现场可编程门阵列（FPGA）。 本发明包括映射单元，其是可能与可重新配置的存储器件组合的电路。 电路具有作为输入的z位源字，其在每个位位置具有值，并且其输出n位输出字，其中n> z，其中n位输出字的每个位位置的值基于 通过选择器地址选择所述预选硬连线位位置的x位字中的预选硬连线位之一的值。 本发明可以包括基于输入到第二存储器设备的x位源地址输出z位源字的第二可重构存储器件，其中x
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