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公开(公告)号:US20210318740A1
公开(公告)日:2021-10-14
申请号:US16947446
申请日:2020-07-31
IPC分类号: G06F1/3203 , G06F1/10 , G06F1/08
摘要: A system includes a first and a second group of cores in a multicore system. Each core of the first/second group is configured to process data. Each core within the first/second group is configured to enter into an idle state in response to being idle for a first/second period of time respectively. Every idle core in the first/second group is configured to transition out of the idle state and into an operational mode in response to receiving a signal having a first/second value respectively and further in response to having a pending operation to process.
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公开(公告)号:US11181967B2
公开(公告)日:2021-11-23
申请号:US16947445
申请日:2020-07-31
IPC分类号: G06F1/32 , G06F1/08 , G06F1/3287
摘要: A system includes a plurality of cores. Each core includes a processing unit, an on-chip memory (OCM), and an idle detector unit. Data is received and stored in the OCM. Instructions are received to process data in the OCM. The core enters an idle mode if the idle detector unit detects that the core has been idle for a first number of clocking signals. The core receives a command to process when in idle mode and transitions from the idle mode to an operational mode. A number of no operation (No-Op) commands is inserted for each time segment. A No-Op command prevents the core from processing instructions for a certain number of clocking signals. A number of No-Op commands inserted for a first time segment is greater than a number of No-Op commands inserted for a last time segment. After the last time segment no No-Op command is inserted.
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