公开(公告)号：US08531903B1

公开(公告)日：2013-09-10

申请号：US13752121

申请日：2013-01-28

Applicant: Marvell International, Ltd.

Inventor： Aditya Ramamoorthy ,  Gregory Burd ,  Xueshi Yang

IPC: G11C7/02

CPC classification number: G11C7/02 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C11/5671 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0033 ,  G11C13/0069 ,  G11C29/00

Abstract: A memory arrangement including a memory block and a controller. The memory block comprises a plurality of memory cells, wherein each memory cell operable to store one of a plurality of different levels of charge. The controller is configured to write (i) a first reference signal threshold into a first memory cell and (ii) a second reference signal threshold into a second memory cell. The first reference signal threshold corresponds to a first level of charge of the plurality of different levels of charge, and the second reference signal threshold corresponds to a second level of charge of the plurality of different levels of charge. Each of the first level of charge and the second level of charge is used to calibrate a read back of any of the one of the plurality of different levels of charge stored among the plurality of memory cells in the memory block.

Abstract translation: 一种包括存储块和控制器的存储装置。 存储器块包括多个存储器单元，其中每个存储器单元可操作以存储多个不同电荷电平中的一个。 控制器被配置为将（i）第一参考信号阈值写入第一存储器单元，以及将第二参考信号阈值写入第二存储单元。 第一参考信号阈值对应于多个不同电荷电平的第一电荷电平，并且第二参考信号阈值对应于多个不同电荷电平的第二电荷电平。 第一级电荷和第二级电荷中的每一种用于校准存储在存储器块中的多个存储器单元之间的多个不同电荷电荷中的任何一个电荷的回读。

公开(公告)号：US08762809B1

公开(公告)日：2014-06-24

申请号：US13942183

申请日：2013-07-15

Applicant: Marvell International Ltd.

Inventor： Adina Matache ,  Heng Tang ,  Gregory Burd ,  Aditya Ramamoorthy ,  Jun Xu ,  Zining Wu

IPC: H03M13/00

CPC classification number: H03M13/1177 ,  H03M13/116 ,  H03M13/1188

Abstract: An apparatus includes a circuit configured to at least one of (i) encode first data to produce encoded data or (ii) decode second data to produce decoded data. The circuit is configured to operate according to a predetermined matrix. Each element of the predetermined matrix labeled with a hyphen corresponds to a zero matrix. Each element of the predetermined matrix labeled with a number corresponds to a respective cyclic-permutation matrix.

Abstract translation: 一种装置包括被配置为（i）编码第一数据以产生编码数据或（ii）解码第二数据以产生解码数据中的至少一个的电路。 电路被配置为根据预定矩阵进行操作。 用连字符标记的预定矩阵的每个元素对应于零矩阵。 用数字标注的预定矩阵的每个元素对应于相应的循环置换矩阵。

公开(公告)号：US09009560B1

公开(公告)日：2015-04-14

申请号：US14309319

申请日：2014-06-19

Applicant: Marvell International Ltd.

Inventor： Adina Matache ,  Heng Tang ,  Gregory Burd ,  Aditya Ramamoorthy ,  Jun Xu ,  Zining Wu

IPC: H03M13/00 ,  H03M13/11

CPC classification number: H03M13/1177 ,  H03M13/116 ,  H03M13/1188

Abstract: An apparatus includes a circuit configured to at least one of (i) encode first data to produce encoded data or (ii) decode second data to produce decoded data. The circuit is configured to operate according to a predetermined matrix. The predetermined matrix is represented by a two-dimensional grid of elements. Each element of the predetermined matrix labeled with a hyphen corresponds to a zero matrix. Each element of the predetermined matrix labeled with a number corresponds to a respective cyclic-permutation matrix.

Abstract translation: 一种装置包括被配置为（i）编码第一数据以产生编码数据或（ii）解码第二数据以产生解码数据中的至少一个的电路。 电路被配置为根据预定矩阵进行操作。 预定矩阵由元素的二维网格表示。 用连字符标记的预定矩阵的每个元素对应于零矩阵。 用数字标注的预定矩阵的每个元素对应于相应的循环置换矩阵。

公开(公告)号：US08693275B1

公开(公告)日：2014-04-08

申请号：US14021712

申请日：2013-09-09

Applicant: Marvell International Ltd.

Inventor： Aditya Ramamoorthy ,  Gregory Burd ,  Xueshi Yang

IPC: G11C7/02

CPC classification number: G11C7/02 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C11/5671 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0033 ,  G11C13/0069 ,  G11C29/00

Abstract: A memory arrangement including a memory block and a controller. The memory block comprises a plurality of memory cells, wherein each memory cell operable to store one of a plurality of different levels of charge. The controller is configured to write (i) a first reference signal threshold into a first memory cell and (ii) a second reference signal threshold into a second memory cell. The first reference signal threshold corresponds to a first level of charge of the plurality of different levels of charge, and the second reference signal threshold corresponds to a second level of charge of the plurality of different levels of charge. Each of the first level of charge and the second level of charge is used to calibrate a read back of any of the one of the plurality of different levels of charge stored among the plurality of memory cells in the memory block.

Abstract translation: 一种包括存储块和控制器的存储装置。 存储器块包括多个存储器单元，其中每个存储器单元可操作以存储多个不同电荷电平中的一个。 控制器被配置为将（i）第一参考信号阈值写入第一存储器单元，以及将第二参考信号阈值写入第二存储单元。 第一参考信号阈值对应于多个不同电荷电平的第一电荷电平，并且第二参考信号阈值对应于多个不同电荷电平的第二电荷电平。 第一级电荷和第二级电荷中的每一种用于校准存储在存储器块中的多个存储器单元之间的多个不同电荷电荷中的任何一个电荷的回读。