公开(公告)号：US10218341B2

公开(公告)日：2019-02-26

申请号：US15812780

申请日：2017-11-14

Applicant: Marvell World Trade Ltd.

Inventor： Luns Tee ,  Wanghua Wu ,  Xiang Gao

IPC: H03K5/135 ,  H03L7/099 ,  H03L7/10 ,  H03L7/18 ,  H03L7/197 ,  H03L7/23

Abstract: Embodiments described herein provide a system having phase synchronized local oscillator paths. The system includes a first circuit, which in turn includes a first counter configured to generate a first counter output signal in response to a first clock signal controlling the first counter. The first circuit also includes a first phase-locked loop coupled to the first counter. The first phase-locked loop is configured to receive the first counter output signal as a first synchronization clock for the first phase-locked loop and to generate a first output signal having rising edges aligned according to the first counter output signal.

公开(公告)号：US20180138899A1

公开(公告)日：2018-05-17

申请号：US15812780

申请日：2017-11-14

Applicant: Marvell World Trade Ltd.

Inventor： Luns Tee ,  Wanghua Wu ,  Xiang Gao

IPC: H03K5/135 ,  H03L7/099

CPC classification number: H03K5/135 ,  H03L7/0992 ,  H03L7/10 ,  H03L7/18 ,  H03L7/1974 ,  H03L7/1976 ,  H03L7/23 ,  H03L2207/06 ,  H03L2207/12

Abstract: Embodiments described herein provide a system having phase synchronized local oscillator paths. The system includes a first circuit, which in turn includes a first counter configured to generate a first counter output signal in response to a first clock signal controlling the first counter. The first circuit also includes a first phase-locked loop coupled to the first counter. The first phase-locked loop is configured to receive the first counter output signal as a first synchronization clock for the first phase-locked loop and to generate a first output signal having rising edges aligned according to the first counter output signal.

公开(公告)号：US20190393867A1

公开(公告)日：2019-12-26

申请号：US16284773

申请日：2019-02-25

Applicant: Marvell World Trade Ltd.

Inventor： Luns Tee ,  Wanghua Wu ,  Xiang Gao

IPC: H03K5/135 ,  H03L7/099 ,  H03L7/23 ,  H03L7/197 ,  H03L7/18 ,  H03L7/10

Abstract: Embodiments described herein provide a system having phase synchronized local oscillator paths. The system includes a first circuit, which in turn includes a first counter configured to generate a first counter output signal in response to a first clock signal controlling the first counter. The first circuit also includes a first phase-locked loop coupled to the first counter. The first phase-locked loop is configured to receive the first counter output signal as a first synchronization clock for the first phase-locked loop and to generate a first output signal having rising edges aligned according to the first counter output signal.