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公开(公告)号：US08232543B2
公开(公告)日：2012-07-31
申请号：US12987606
申请日：2011-01-10
IPC分类号： H01L31/032 , H01L45/00
CPC分类号： H01L45/144 , G11C11/5678 , G11C13/0004 , G11C2213/79 , H01L27/2436 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/1675
摘要： A semiconductor device and a method of manufacturing the same with easy formation of a phase change film is realized, realizing high integration at the time of using a phase change film as a memory element.Between MISFET of the region which forms one memory cell, and MISFET which adjoined it, each source of MISFET adjoins in the front surface of a semiconductor substrate, insulating. And the multi-layer structure of a phase change film, and the electric conduction film of specific resistance lower than the specific resistance is formed in the plan view of the front surface of a semiconductor substrate ranging over each source of both MISFET, and a plug and a plug stacked on it. The multi-layer structure functions as a wiring extending and existing in parallel on the surface of a semiconductor substrate, and an electric conduction film sends the current of a parallel direction on the surface of a semiconductor substrate.
摘要翻译： 实现了容易形成相变膜的半导体器件及其制造方法，在使用相变膜作为存储元件时实现高集成度。 在形成一个存储单元的区域的MISFET和与其相邻的MISFET之间，MISFET的每个源极邻接在半导体衬底的前表面中，绝缘。 并且在两个MISFET的每个源上的半导体衬底的前表面的平面图中形成相变膜的多层结构和比电阻率低的电阻率的导电膜，并且插塞 和堆叠在其上的插头。 多层结构用作在半导体衬底的表面上平行延伸并存在的布线，并且导电膜在半导体衬底的表面上发送平行方向的电流。
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公开(公告)号：US08546783B2
公开(公告)日：2013-10-01
申请号：US13541097
申请日：2012-07-03
IPC分类号： H01L31/032 , H01L45/00
CPC分类号： H01L45/144 , G11C11/5678 , G11C13/0004 , G11C2213/79 , H01L27/2436 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/1675
摘要： A semiconductor device and a method of manufacturing the same with easy formation of a phase change film is realized, realizing high integration and using a phase change film as a memory element. Between a MISFET of a region forming one memory cell and an adjoining MISFET, each MISFET source adjoins in the front surface of an insulating semiconductor substrate. A multi-layer structure of a phase change film and electric conduction film of specific resistance lower than the specific resistance is formed in plan view of the front surface of a semiconductor substrate ranging over each source of both MISFETs, and a plug is stacked thereon. The multi-layer structure functions as a wiring extending and existing in parallel on the surface of the semiconductor substrate, and an electric conduction film sends current in a parallel direction on the surface of the semiconductor substrate.
摘要翻译： 实现了容易形成相变膜的半导体器件及其制造方法，实现了高集成度和使用相变膜作为存储元件。 在形成一个存储单元的区域的MISFET与相邻的MISFET之间，每个MISFET源在绝缘半导体衬底的前表面相邻。 在两个MISFET的每个源极上的半导体衬底的前表面的平面图中形成具有比电阻率低的电阻率的相变膜和导电膜的多层结构，并且在其上层叠插塞。 多层结构用作在半导体衬底的表面上平行延伸并存在的布线，并且导电膜在半导体衬底的表面上沿平行方向发送电流。
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公开(公告)号：US20110101297A1
公开(公告)日：2011-05-05
申请号：US12987606
申请日：2011-01-10
IPC分类号： H01L45/00
CPC分类号： H01L45/144 , G11C11/5678 , G11C13/0004 , G11C2213/79 , H01L27/2436 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/1675
摘要： A semiconductor device and a method of manufacturing the same with easy formation of a phase change film is realized, realizing high integration at the time of using a phase change film as a memory element.Between MISFET of the region which forms one memory cell, and MISFET which adjoined it, each source of MISFET adjoins in the front surface of a semiconductor substrate, insulating. And the multi-layer structure of a phase change film, and the electric conduction film of specific resistance lower than the specific resistance is formed in the plan view of the front surface of a semiconductor substrate ranging over each source of both MISFET, and a plug and a plug stacked on it. The multi-layer structure functions as a wiring extending and existing in parallel on the surface of a semiconductor substrate, and an electric conduction film sends the current of a parallel direction on the surface of a semiconductor substrate.
摘要翻译： 实现了容易形成相变膜的半导体器件及其制造方法，在使用相变膜作为存储元件时实现高集成度。 在形成一个存储单元的区域的MISFET和与其相邻的MISFET之间，MISFET的每个源极邻接在半导体衬底的前表面中，绝缘。 并且在两个MISFET的每个源上的半导体衬底的前表面的平面图中形成相变膜的多层结构和比电阻率低的电阻率的导电膜，并且插塞 和堆叠在其上的插头。 多层结构用作在半导体衬底的表面上平行延伸并存在的布线，并且导电膜在半导体衬底的表面上发送平行方向的电流。
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公开(公告)号：US07714314B2
公开(公告)日：2010-05-11
申请号：US11775474
申请日：2007-07-10
IPC分类号： H01L29/02 , H01L31/032
CPC分类号： H01L45/144 , G11C11/5678 , G11C13/0004 , G11C2213/79 , H01L27/2436 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/1675
摘要： A semiconductor device and a method of manufacturing the same with easy formation of a phase change film is realized, realizing high integration at the time of using a phase change film as a memory element.Between MISFET of the region which forms one memory cell, and MISFET which adjoined it, each source of MISFET adjoins in the front surface of a semiconductor substrate, insulating. And the multi-layer structure of a phase change film, and the electric conduction film of specific resistance lower than the specific resistance is formed in the plan view of the front surface of a semiconductor substrate ranging over each source of both MISFET, and a plug and a plug stacked on it. The multi-layer structure functions as a wiring extending and existing in parallel on the surface of a semiconductor substrate, and an electric conduction film sends the current of a parallel direction on the surface of a semiconductor substrate.
摘要翻译： 实现了容易形成相变膜的半导体器件及其制造方法，在使用相变膜作为存储元件时实现高集成度。 在形成一个存储单元的区域的MISFET和与其相邻的MISFET之间，MISFET的每个源极邻接在半导体衬底的前表面中，绝缘。 并且在两个MISFET的每个源上的半导体衬底的前表面的平面图中形成相变膜的多层结构和比电阻率低的电阻率的导电膜，并且插塞 和堆叠在其上的插头。 多层结构用作在半导体衬底的表面上平行延伸并存在的布线，并且导电膜在半导体衬底的表面上发送平行方向的电流。
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公开(公告)号：US20080011997A1
公开(公告)日：2008-01-17
申请号：US11775474
申请日：2007-07-10
IPC分类号： H01L45/00
CPC分类号： H01L45/144 , G11C11/5678 , G11C13/0004 , G11C2213/79 , H01L27/2436 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/1675
摘要： A semiconductor device and a method of manufacturing the same with easy formation of a phase change film is realized, realizing high integration at the time of using a phase change film as a memory element.Between MISFET of the region which forms one memory cell, and MISFET which adjoined it, each source of MISFET adjoins in the front surface of a semiconductor substrate, insulating. And the multi-layer structure of a phase change film, and the electric conduction film of specific resistance lower than the specific resistance is formed in the plan view of the front surface of a semiconductor substrate ranging over each source of both MISFET, and a plug and a plug stacked on it. The multi-layer structure functions as a wiring extending and existing in parallel on the surface of a semiconductor substrate, and an electric conduction film sends the current of a parallel direction on the surface of a semiconductor substrate.
摘要翻译： 实现了容易形成相变膜的半导体器件及其制造方法，在使用相变膜作为存储元件时实现高集成度。 在形成一个存储单元的区域的MISFET和与其相邻的MISFET之间，MISFET的每个源极邻接在半导体衬底的前表面中，绝缘。 并且在两个MISFET的每个源上的半导体衬底的前表面的平面图中形成相变膜的多层结构和比电阻率低的电阻率的导电膜，并且插塞 和堆叠在其上的插头。 多层结构用作在半导体衬底的表面上平行延伸并存在的布线，并且导电膜在半导体衬底的表面上发送平行方向的电流。
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公开(公告)号：US20120286225A1
公开(公告)日：2012-11-15
申请号：US13541097
申请日：2012-07-03
IPC分类号： H01L45/00
CPC分类号： H01L45/144 , G11C11/5678 , G11C13/0004 , G11C2213/79 , H01L27/2436 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/1675
摘要： A semiconductor device and a method of manufacturing the same with easy formation of a phase change film is realized, realizing high integration and using a phase change film as a memory element. Between a MISFET of a region forming one memory cell and an adjoining MISFET, each MISFET source adjoins in the front surface of an insulating semiconductor substrate. A multi-layer structure of a phase change film and electric conduction film of specific resistance lower than the specific resistance is formed in plan view of the front surface of a semiconductor substrate ranging over each source of both MISFETs, and a plug is stacked thereon. The multi-layer structure functions as a wiring extending and existing in parallel on the surface of the semiconductor substrate, and an electric conduction film sends current in a parallel direction on the surface of the semiconductor substrate.
摘要翻译： 实现了容易形成相变膜的半导体器件及其制造方法，实现了高集成度和使用相变膜作为存储元件。 在形成一个存储单元的区域的MISFET与相邻的MISFET之间，每个MISFET源在绝缘半导体衬底的前表面相邻。 在两个MISFET的每个源极上的半导体衬底的前表面的平面图中形成具有比电阻率低的电阻率的相变膜和导电膜的多层结构，并且在其上层叠插塞。 多层结构用作在半导体衬底的表面上平行延伸并存在的布线，并且导电膜在半导体衬底的表面上沿平行方向发送电流。
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公开(公告)号：US07884348B2
公开(公告)日：2011-02-08
申请号：US12754049
申请日：2010-04-05
IPC分类号： H01L29/02 , H01L31/032
CPC分类号： H01L45/144 , G11C11/5678 , G11C13/0004 , G11C2213/79 , H01L27/2436 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/1675
摘要： A semiconductor device and a method of manufacturing the same with easy formation of a phase change film is realized, realizing high integration at the time of using a phase change film as a memory element.Between MISFET of the region which forms one memory cell, and MISFET which adjoined it, each source of MISFET adjoins in the front surface of a semiconductor substrate, insulating. And the multi-layer structure of a phase change film, and the electric conduction film of specific resistance lower than the specific resistance is formed in the plan view of the front surface of a semiconductor substrate ranging over each source of both MISFET, and a plug and a plug stacked on it. The multi-layer structure functions as a wiring extending and existing in parallel on the surface of a semiconductor substrate, and an electric conduction film sends the current of a parallel direction on the surface of a semiconductor substrate.
摘要翻译： 实现了容易形成相变膜的半导体器件及其制造方法，在使用相变膜作为存储元件时实现高集成度。 在形成一个存储单元的区域的MISFET和与其相邻的MISFET之间，MISFET的每个源极邻接在半导体衬底的前表面中，绝缘。 并且在两个MISFET的每个源上的半导体衬底的前表面的平面图中形成相变膜的多层结构和比电阻率低的电阻率的导电膜，并且插塞 和堆叠在其上的插头。 多层结构用作在半导体衬底的表面上平行延伸并存在的布线，并且导电膜在半导体衬底的表面上发送平行方向的电流。
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公开(公告)号：US20100193764A1
公开(公告)日：2010-08-05
申请号：US12754049
申请日：2010-04-05
IPC分类号： H01L45/00 , H01L27/105
CPC分类号： H01L45/144 , G11C11/5678 , G11C13/0004 , G11C2213/79 , H01L27/2436 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/1675
摘要： A semiconductor device and a method of manufacturing the same with easy formation of a phase change film is realized, realizing high integration at the time of using a phase change film as a memory element.Between MISFET of the region which forms one memory cell, and MISFET which adjoined it, each source of MISFET adjoins in the front surface of a semiconductor substrate, insulating. And the multi-layer structure of a phase change film, and the electric conduction film of specific resistance lower than the specific resistance is formed in the plan view of the front surface of a semiconductor substrate ranging over each source of both MISFET, and a plug and a plug stacked on it. The multi-layer structure functions as a wiring extending and existing in parallel on the surface of a semiconductor substrate, and an electric conduction film sends the current of a parallel direction on the surface of a semiconductor substrate.
摘要翻译： 实现了容易形成相变膜的半导体器件及其制造方法，在使用相变膜作为存储元件时实现高集成度。 在形成一个存储单元的区域的MISFET和与其相邻的MISFET之间，MISFET的每个源极邻接在半导体衬底的前表面中，绝缘。 并且在两个MISFET的每个源上的半导体衬底的前表面的平面图中形成相变膜的多层结构和比电阻率低的电阻率的导电膜，并且插塞 和堆叠在其上的插头。 多层结构用作在半导体衬底的表面上平行延伸并存在的布线，并且导电膜在半导体衬底的表面上发送平行方向的电流。
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9.发明申请Semiconductor device with a non-erasable memory and/or a nonvolatile memory 失效具有不可擦除存储器和/或非易失性存储器的半导体器件公开(公告)号：US20070159871A1
公开(公告)日：2007-07-12
申请号：US11715918
申请日：2007-03-09
CPC分类号： G11C13/0004 , G11C13/0033 , G11C13/004 , G11C13/0064 , G11C13/0069 , G11C16/3454 , G11C2013/0092 , G11C2213/82
摘要： A semiconductor device comprises a plurality of memory cells, a central processing unit, a timer circuit which times a RESET time, and a timer circuit which times a SET time. A threshold voltage of an NMOS transistor of each memory cell is lower than that of the peripheral circuit, thereby easily executing a RESET operation. The direction of a flowing current is changed across the RESET operation and the SET operation, and the bit lines are activated at high speed, thus preventing system malfunctions. Further, the semiconductor device can overcome such problems as a wrong write operation and data destruction, resulting from the variation in the CMOS transistors when operating phase change elements with minimum size CMOS transistors at a core voltage (e.g. 1.2 V). According to the present invention, stable operations can be realized at a low voltage, using minimum-size cell transistors.
摘要翻译： 一种半导体器件包括多个存储单元，一个中央处理单元，一个复位时间的定时器电路，以及一个定时器电路，该定时器电路需要一个SET时间。 每个存储单元的NMOS晶体管的阈值电压低于外围电路的阈值电压，从而容易地执行复位操作。 流过电流的方向在复位操作和SET操作中改变，位线被高速激活，从而防止系统故障。 此外，半导体器件可以克服由于核心电压（例如1.2V）下操作具有最小尺寸CMOS晶体管的相位变化元件时CMOS晶体管的变化而导致的错误写入操作和数据破坏的问题。 根据本发明，可以使用最小尺寸的单元晶体管在低电压下实现稳定的操作。
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公开(公告)号：US07206216B2
公开(公告)日：2007-04-17
申请号：US11057682
申请日：2005-02-15
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C13/0033 , G11C13/004 , G11C13/0064 , G11C13/0069 , G11C16/3454 , G11C2013/0092 , G11C2213/82
摘要： A semiconductor device comprises a plurality of memory cells, a central processing unit, a timer circuit which times a RESET time, and a timer circuit which times a SET time. A threshold voltage of an NMOS transistor of each memory cell is lower than that of the peripheral circuit, thereby easily executing a RESET operation. The direction of a flowing current is changed across the RESET operation and the SET operation, and the bit lines are activated at high speed, thus preventing system malfunctions. Further, the semiconductor device can overcome such problems as a wrong write operation and data destruction, resulting from the variation in the CMOS transistors when operating phase change elements with minimum size CMOS transistors at a core voltage (e.g. 1.2 V). According to the present invention, stable operations can be realized at a low voltage, using minimum-size cell transistors.
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