公开(公告)号：US20060212680A1

公开(公告)日：2006-09-21

申请号：US11344403

申请日：2006-01-31

申请人： Masahiro Yasue ,  Akiyuki Hatakeyama

发明人： Masahiro Yasue ,  Akiyuki Hatakeyama

IPC分类号： G06F9/30

CPC分类号： G06F9/3846 ,  G06F9/30047 ,  G06F9/30072 ,  G06F9/3804

摘要： A method, storage medium, processor instruction and processor to for specifying a value in a first portion of a conditional pre-fetch instruction associated with a branch instruction used for effectuating a branch operation, specifying a target instruction address in a second portion of the instruction, evaluating the value to determine whether a condition is met, and pre-fetching one or more instructions starting at the target instruction address into an instruction buffer of the processor when the condition is met, is provided.

公开(公告)号：US20090313456A1

公开(公告)日：2009-12-17

申请号：US12540522

申请日：2009-08-13

申请人： Masahiro Yasue ,  Akiyuki Hatakeyama

发明人： Masahiro Yasue ,  Akiyuki Hatakeyama

IPC分类号： G06F9/38

CPC分类号： G06F9/3846 ,  G06F9/30047 ,  G06F9/30072 ,  G06F9/3804

摘要： A method, storage medium, processor instruction and processor to for specifying a value in a first portion of a conditional pre-fetch instruction associated with a branch instruction used for effectuating a branch operation, specifying a target instruction address in a second portion of the instruction, evaluating the value to determine whether a condition is met, and pre-fetching one or more instructions starting at the target instruction address into an instruction buffer of the processor when the condition is met, is provided.

摘要翻译： 一种用于指定与用于实现分支操作的分支指令相关联的条件预取指令的第一部分中的值的方法，存储介质，处理器指令和处理器，在指令的第二部分中指定目标指令地址 提供该值，以确定是否满足条件，并且在满足条件时将从目标指令地址开始的一个或多个指令预取到处理器的指令缓冲器中。

公开(公告)号：US07627740B2

公开(公告)日：2009-12-01

申请号：US11344403

申请日：2006-01-31

申请人： Masahiro Yasue ,  Akiyuki Hatakeyama

发明人： Masahiro Yasue ,  Akiyuki Hatakeyama

IPC分类号： G06F9/312

CPC分类号： G06F9/3846 ,  G06F9/30047 ,  G06F9/30072 ,  G06F9/3804

摘要： A method, storage medium, processor instruction and processor to for specifying a value in a first portion of a conditional pre-fetch instruction associated with a branch instruction used for effectuating a branch operation, specifying a target instruction address in a second portion of the instruction, evaluating the value to determine whether a condition is met, and pre-fetching one or more instructions starting at the target instruction address into an instruction buffer of the processor when the condition is met, is provided.

摘要翻译： 一种用于指定与用于实现分支操作的分支指令相关联的条件预取指令的第一部分中的值的方法，存储介质，处理器指令和处理器，在指令的第二部分中指定目标指令地址 提供该值，以确定是否满足条件，并且在满足条件时将从目标指令地址开始的一个或多个指令预取到处理器的指令缓冲器中。

公开(公告)号：US08250344B2

公开(公告)日：2012-08-21

申请号：US12540522

申请日：2009-08-13

申请人： Masahiro Yasue ,  Akiyuki Hatakeyama

发明人： Masahiro Yasue ,  Akiyuki Hatakeyama

IPC分类号： G06F9/312

CPC分类号： G06F9/3846 ,  G06F9/30047 ,  G06F9/30072 ,  G06F9/3804

摘要： A method, storage medium, processor instruction and processor to for specifying a value in a first portion of a conditional pre-fetch instruction associated with a branch instruction used for effectuating a branch operation, specifying a target instruction address in a second portion of the instruction, evaluating the value to determine whether a condition is met, and pre-fetching one or more instructions starting at the target instruction address into an instruction buffer of the processor when the condition is met, is provided.

摘要翻译： 一种用于指定与用于实现分支操作的分支指令相关联的条件预取指令的第一部分中的值的方法，存储介质，处理器指令和处理器，在指令的第二部分中指定目标指令地址 提供该值，以确定是否满足条件，并且在满足条件时将从目标指令地址开始的一个或多个指令预取到处理器的指令缓冲器中。

公开(公告)号：US08271805B2

公开(公告)日：2012-09-18

申请号：US11344654

申请日：2006-02-01

申请人： Masahiro Yasue

发明人： Masahiro Yasue

IPC分类号： G06F21/00

CPC分类号： H04L9/00 ,  G06F21/31 ,  G06F21/72 ,  G06F21/79 ,  G06F2221/2143 ,  H04N21/4405 ,  H04N21/44055

摘要： The present invention provides a secure buffer for use in data storage and encryption processing. Blocks or packets of data are passed to a secure buffer within a processor. The processor may be one of many coprocessors, and the secure buffer may be inaccessible to some or all of the coprocessors. Data may be partially or fully encrypted and stored within the secure buffer. Encryption may occur before or after storage in the buffer, or it may take place within the buffer itself. Optionally, the encrypted data may be sent to and retrieved from a shared memory that is accessible by other coprocessors.

摘要翻译： 本发明提供一种用于数据存储和加密处理的安全缓冲器。 数据块或数据包传递到处理器内的安全缓冲区。 处理器可以是许多协处理器之一，并且安全缓冲器可能对于一些或所有协处理器是不可访问的。 数据可能部分或完全加密并存储在安全缓冲区内。 在缓冲区中存储之前或之后可能会发生加密，也可能在缓冲区内发生加密。 可选地，可以将加密的数据发送到可由其他协处理器访问的共享存储器并从其恢复。

公开(公告)号：US20080170080A1

公开(公告)日：2008-07-17

申请号：US11950864

申请日：2007-12-05

申请人： Tatsuya Ishiwata ,  Masahiro Yasue

发明人： Tatsuya Ishiwata ,  Masahiro Yasue

IPC分类号： G06F15/16 ,  G06T15/70

CPC分类号： G06T1/20 ,  G06T19/00 ,  G06T2210/21 ,  G06T2210/52 ,  Y10S345/958

摘要： A parallelization permission and prohibition management unit of a processor manages the permission or prohibition of the parallelization for each combination of partial spaces in cooperation with another parallelization permission and prohibition management unit of a different processor. Specifically, when any given object is present across the boundary between a first partial space and a second partial space, the parallelization is prohibited between the collision process to be performed by any given processor on the virtual objects in the first partial space and the collision process to be performed by another processor on the virtual object in the second partial space.

摘要翻译： 处理器的并行化许可和禁止管理单元与不同处理器的另一个并行化许可和禁止管理单元协同管理对每个组合的部分空间进行并行化的许可或禁止。 具体地说，当在第一部分空间和第二部分空间之间的边界上存在任何给定对象时，在由第一部分空间中的虚拟对象上的任何给定处理器执行的冲突处理与冲突处理之间禁止并行化 由第二部分空间中的虚拟对象上的另一处理器执行。

公开(公告)号：US20060200610A1

公开(公告)日：2006-09-07

申请号：US11346947

申请日：2006-02-03

申请人： Masahiro Yasue ,  Keisuke Inoue

发明人： Masahiro Yasue ,  Keisuke Inoue

IPC分类号： G06F13/26

CPC分类号： G06F9/4812 ,  G06F13/26

摘要： A multiprocessor system and method wherein one of the processors is assigned the responsibility of handling interrupts and identifying the next processor to handle an interrupt. When that processor switches tasks and determines that it is no longer the least important processor as far as task priority is concerned, it will then select and transfer its interrupt-related responsibilities (i.e., handling the interrupt and determining the next interrupt-handing processor) to the processor which is executing the least important task. The selected processor will then be designated for handling interrupts unless and until it undergoes a task switch and selects a different processor.

摘要翻译： 一种多处理器系统和方法，其中处理器之一被分配处理中断的责任并识别下一个处理器来处理中断。 当处理器切换任务并确定它不再是任务优先级中最不重要的处理器时，它将选择并传递其与中断有关的职责（即处理中断并确定下一个中断处理器） 到执行最不重要任务的处理器。 然后，所选择的处理器将被指定用于处理中断，除非和直到它进行任务切换并选择不同的处理器。

公开(公告)号：US07882310B2

公开(公告)日：2011-02-01

申请号：US12113366

申请日：2008-05-01

申请人： Keisuke Inoue ,  Masahiro Yasue

发明人： Keisuke Inoue ,  Masahiro Yasue

IPC分类号： G06F12/00

CPC分类号： G06F12/023 ,  G06F12/0284

摘要： Methods and apparatus provide for associating memory allocation table (MAT) entries with nodes in a binary tree such that the nodes and the entries are grouped into hierarchical levels, each entry including status information; associating the nodes and the entries with segments of a shared memory of a multi-processor system such that higher level nodes and entries are associated with larger numbers of segments of the shared memory and lower level nodes and entries are associated with smaller numbers of segments of the shared memory; initializing the MAT such that the status information of at least a plurality of entries indicates that the associated segment or segments of the shared memory are available for reservation; and selecting one entry in a group of entries in the MAT at a level corresponding to a desired size of the shared memory to be reserved.

摘要翻译： 方法和装置提供将存储器分配表（MAT）条目与二进制树中的节点相关联，使得节点和条目被分组成层级，每个条目包括状态信息; 将节点和条目与多处理器系统的共享存储器的段相关联，使得较高级节点和条目与共享存储器的较大数量的段相关联，并且较低级节点和条目与较少数量的段 共享内存; 初始化MAT，使得至少多个条目的状态信息指示共享存储器的相关联的段或段可用于预留; 以及在与要保留的共享存储器的期望大小相对应的级别的MAT中选择一组条目中的一个条目。

公开(公告)号：US07646923B2

公开(公告)日：2010-01-12

申请号：US11045774

申请日：2005-01-28

申请人： Masahiro Yasue

发明人： Masahiro Yasue

IPC分类号： G06K9/36

CPC分类号： H04N19/182 ,  H04N19/12 ,  H04N19/14

摘要： A method of and apparatus for compressing a stream of data, such as video data, is disclosed. First, data in the video stream are classified in accordance with their values. Data with values equal to zero are classified in a first class. Data with values less than a predetermined positive number but greater than a predetermined negative number, and not equal to zero, are classified in a second class. All other data are classified in a third class. Data in the first class is compressed using a run length encoding technique. Data in the second class is compressed by reducing the size of the data value and by adding a constant. Data in the third class is not compressed, but is modified by adding a constant. The data can be decompressed by determining the class of the compressed value and reversing the compression process. The compression method disclosed is easy to implement and results in a significant reduction in the amount of data that needs to be transmitted.

摘要翻译： 公开了一种用于压缩诸如视频数据的数据流的方法和装置。 首先，视频流中的数据根据​​它们的值进行分类。 值等于零的数据分类为第一类。 具有小于预定正数但大于预定负数但大于等于零的值的数据被分类为第二类。 所有其他数据都分为第三类。 使用游程长度编码技术来压缩第一类中的数据。 通过减小数据值的大小并添加常量来压缩第二类中的数据。 第三类中的数据不被压缩，但是通过添加常量来修改。 可以通过确定压缩值的类并反转压缩过程来解压缩数据。 所公开的压缩方法易于实现，并且导致需要传输的数据量的显着减少。

公开(公告)号：US07614053B2

公开(公告)日：2009-11-03

申请号：US10783246

申请日：2004-02-20

申请人： Keisuke Inoue ,  Tatsuya Iwamoto ,  Masahiro Yasue

发明人： Keisuke Inoue ,  Tatsuya Iwamoto ,  Masahiro Yasue

IPC分类号： G06F9/455 ,  G06F9/46

CPC分类号： G06F9/4881 ,  G06F9/4411 ,  G06F9/5038 ,  G06F2209/483 ,  G06F2209/484

摘要： Methods and apparatus are provided for managing processor tasks in a multi-processor computing system. The system is operable to store the processor tasks in a shared memory that may be accessed by a plurality of sub-processing units of the multi-processor computing system; and permit the sub-processing units to determine which of the processor tasks should be copied from the shared memory and executed based on priorities of the processor tasks.

摘要翻译： 提供了用于在多处理器计算系统中管理处理器任务的方法和装置。 该系统可操作以将处理器任务存储在可由多处理器计算系统的多个子处理单元访问的共享存储器中; 并且允许子处理单元基于处理器任务的优先级来确定应该从共享存储器复制哪个处理器任务并执行。