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    Multiple sequentially transferrable stackpointers in a data processor in a pipelining system
    5.
    发明授权
    Multiple sequentially transferrable stackpointers in a data processor in a pipelining system 失效
    在流水线系统中的数据处理器中的多个可顺序传输的堆栈指针

    公开(公告)号：US4974158A

    公开(公告)日：1990-11-27

    申请号：US506498

    申请日：1990-04-09

    申请人： Yukari Watanabe ,  Toyohiko Yoshida ,  Masahito Matsuo ,  Yuichi Saito ,  Toru Shimizu

    发明人： Yukari Watanabe ,  Toyohiko Yoshida ,  Masahito Matsuo ,  Yuichi Saito ,  Toru Shimizu

    IPC分类号： G06F9/38

    CPC分类号： G06F9/3824 ,  G06F9/3863 ,  G06F9/3867

    摘要： This invention relates to a data processor with pipelining system, which is provided with at least two stages having working stackpointer respectively, and so constructed that each stage can independently refer to the working stackpointer corresponding to each stage, and each working stackpointer corresponding to each stage is renewed synchronizing with pipelining processing, so that when execution of a plural instructions including designation of operands under stack-push addressing mode and stack-pop addressing mode, result of address calculation executed at the address calculation stage is sequentially transferred to corresponding working stackpointers synchronizing with the transfer of instructions through the stages of pipeline, thereby being possible for the data processor to smoothly execute pipelining process.

    摘要翻译： 本发明涉及一种具有流水线系统的数据处理器，其具有分别具有工作堆栈指针的至少两个级，并且构造成使得每个级可以独立地指代对应于每个级的工作堆栈指针，并且每个工作堆栈指针对应于每个级 与流水线处理同步地更新，使得当在堆栈推送寻址模式和堆栈弹出寻址模式下执行包括指定操作数的多个指令时，在地址计算阶段执行的地址计算的结果被顺序地传送到相应的工作堆栈指针同步 通过管道传送指令，从而可以使数据处理器顺利地执行流水线处理。

    Data processing system capable of executing groups of instructions, including at least one arithmetic instruction, in parallel
    6.
    发明授权
    Data processing system capable of executing groups of instructions, including at least one arithmetic instruction, in parallel 失效
    数据处理系统能够并行地执行包括至少一个算术指令的指令组

    公开(公告)号：US6131158A

    公开(公告)日：2000-10-10

    申请号：US759499

    申请日：1996-12-04

    申请人： Masahito Matsuo ,  Toru Shimizu ,  Toyohiko Yoshida

    发明人： Masahito Matsuo ,  Toru Shimizu ,  Toyohiko Yoshida

    IPC分类号： G06F9/30 ,  G06F9/302 ,  G06F9/38 ,  G06F11/28 ,  G06F11/36

    CPC分类号： G06F9/3865 ,  G06F11/28 ,  G06F11/3648 ,  G06F9/3001 ,  G06F9/30149 ,  G06F9/3822 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3869 ,  G06F9/3875

    摘要： A data processor performs various types of EIT (exception, interrupt, trap) processing in connection with the execution of the preceding and following instructions in parallel. In one embodiment, an exception is detected resulting from processing the previous instruction in the pair being executed in parallel before completion of instruction processing where the exception requires re-execution. When the exception is detected a control means prevents the execution means from executing both preceding and following instructions. An additional feature is a control unit that controls when an interrupt is accepted during parallel execution. In another embodiment, a first decoder outputs suppressing information when the preceding instruction is a predetermined instruction having a possibility of causing a trap. A validity judgment circuit prevents the second decoded result from being issued when suppressing information is generated.

    摘要翻译： 数据处理器并行执行与执行前述和后续指令相关的各种类型的EIT（异常，中断，陷阱）处理。 在一个实施例中，检测到异常，这是由于在执行异常需要重新执行的指令处理完成之前处理在该对中的先前指令并行执行的异常。 当检测到异常时，控制装置防止执行装置执行前述和后续指令。 一个附加功能是控制单元，用于控制在并行执行期间接受中断的时间。 在另一个实施例中，当前一条指令是具有引起陷阱的可能性的预定指令时，第一解码器输出抑制信息。 当产生抑制信息时，有效性判断电路防止发出第二解码结果。

    Multiple sequentially transferrable stackpointers in a data processor in a pipelining system
    7.
    发明授权
    Multiple sequentially transferrable stackpointers in a data processor in a pipelining system 失效
    在流水线系统中的数据处理器中的多个可顺序传输的堆栈指针

    公开(公告)号：US5566307A

    公开(公告)日：1996-10-15

    申请号：US408198

    申请日：1995-03-22

    申请人： Yukari Watanabe ,  Toyohiko Yoshida ,  Masahito Matsuo ,  Yuichi Saito ,  Toru Shimizu

    发明人： Yukari Watanabe ,  Toyohiko Yoshida ,  Masahito Matsuo ,  Yuichi Saito ,  Toru Shimizu

    IPC分类号： G06F9/38

    CPC分类号： G06F9/3824 ,  G06F9/3863 ,  G06F9/3867

    摘要： This invention relates to a data processor with pipelining system, which is provided with at least two stages each having working stackpointers, and so constructed that each stage can independently refer to the working stackpointer corresponding to each stage, and the renewal of each working stackpointer corresponding to each stage occurs synchronously with pipeline processing, so that when execution of a plural instructions including designation of operands under stack-push addressing mode and stack-pop addressing mode, result of address calculation executed at the address calculation stage is sequentially transferred to a corresponding working stackpointer in a next pipeline stage. This is synchronized with the transfer of instructions through the stages of pipeline, thereby being possible for the data processor to smoothly execute pipelining process.

    摘要翻译： 本发明涉及一种具有流水线系统的数据处理器，其具有至少两个阶段，每个阶段具有工作堆栈指针，并且构造成使得每个阶段可以独立地指代对应于每个阶段的工作堆栈指针，并且每个工作堆栈指针对应的更新对应 到每一级与流水线处理同步地发生，从而当执行包括在堆栈推送寻址模式和堆栈弹出寻址模式下操作数的指定的多个指令时，在地址计算阶段执行的地址计算的结果被顺序地传送到相应的 在下一个流水线阶段工作stackpointer。 这与通过流水线的指令的传送同步，从而可以使数据处理器顺利地执行流水线处理。

    Data processor processing a jump instruction
    9.
    发明授权
    Data processor processing a jump instruction 失效
    数据处理器处理跳转指令

    公开(公告)号：US5649145A

    公开(公告)日：1997-07-15

    申请号：US537001

    申请日：1995-09-29

    申请人： Masahito Matsuo ,  Toyohiko Yoshida

    发明人： Masahito Matsuo ,  Toyohiko Yoshida

    IPC分类号： G06F9/32 ,  G06F9/38 ,  G06F9/30

    CPC分类号： G06F9/3804 ,  G06F9/322 ,  G06F9/3842

    摘要： A data processor, comprising: an instruction fetch unit 111 which fetches instructions from a memory which stores instructions; an instruction decoding unit 112 which decodes the instructions fetched from the instruction fetch unit 111; an instruction execution unit which executes the instructions on the basis of the decoding result by the instruction decoding unit 112; a program counter (DPC) 29 which holds an address of the instruction being decoded in the instruction decoding unit 112; and a branch target address calculation unit 1 which is connected to the instruction fetch unit 111 and the program counter (DPC) 29, adds a value of a branch displacement field transferred from the instruction fetch unit 111 and the instruction address transferred from the program counter (DPC) 29, and transfers the addition result to the instruction fetch unit 111, so that jump instruction can be processed efficiently by pipeline processing.

    摘要翻译： 一种数据处理器，包括：指令提取单元111，其从存储指令的存储器中取出指令; 指令解码单元112，对从指令获取单元111取出的指令进行解码; 指令执行单元，其基于指令解码单元112的解码结果执行指令; 程序计数器（DPC）29，其保持在指令解码单元112中解码的指令的地址; 和连接到指令提取单元111和程序计数器（DPC）29的分支目标地址计算单元1相加从指令提取单元111传送的分支位移字段的值和从程序计数器传送的指令地址 （DPC）29，并将相加结果传送到指令提取单元111，使得可以通过流水线处理有效地处理跳转指令。

    Data processor generating jump target address of a jump instruction in parallel with decoding of the instruction
    10.
    发明授权
    Data processor generating jump target address of a jump instruction in parallel with decoding of the instruction 失效
    数据处理器与指令的解码并行地产生跳转指令的跳转目标地址

    公开(公告)号：US5617550A

    公开(公告)日：1997-04-01

    申请号：US535871

    申请日：1995-09-29

    申请人： Masahito Matsuo ,  Toyohiko Yoshida

    发明人： Masahito Matsuo ,  Toyohiko Yoshida

    IPC分类号： G06F9/32 ,  G06F9/38

    CPC分类号： G06F9/3804 ,  G06F9/322 ,  G06F9/3842

    摘要： A data processor, comprising: an instruction fetch unit 111 which fetches instructions from a memory which stores instructions; an instruction decoding unit 112 which decodes the instructions fetched from the instruction fetch unit 111; an instruction execution unit which executes the instructions on the basis of the decoding result by the instruction decoding unit 112; a program counter (DPC) 29 which holds an address of the instruction being decoded in the instruction decoding unit 112; and a branch target address calculation unit 1 which is connected to the instruction fetch unit 111 and the program counter (DPC) 29, adds a value of a branch displacement field transferred from the instruction fetch unit 111 and the instruction address transferred from the program counter (DPC) 29, and transfers the addition result to the instruction fetch unit 111, so that jump instruction can be processed efficiently by pipeline processing.

    摘要翻译： 一种数据处理器，包括：指令提取单元111，其从存储指令的存储器中取出指令; 指令解码单元112，对从指令获取单元111取出的指令进行解码; 指令执行单元，其基于指令解码单元112的解码结果执行指令; 程序计数器（DPC）29，其保持在指令解码单元112中解码的指令的地址; 和连接到指令提取单元111和程序计数器（DPC）29的分支目标地址计算单元1相加从指令提取单元111传送的分支位移字段的值和从程序计数器传送的指令地址 （DPC）29，并将相加结果传送到指令提取单元111，使得可以通过流水线处理有效地处理跳转指令。