公开(公告)号：US5189315A

公开(公告)日：1993-02-23

申请号：US830706

申请日：1992-02-04

申请人： Masao Akata

发明人： Masao Akata

IPC分类号： H03K3/012 ,  H03K3/037 ,  H03K3/3562

CPC分类号： H03K3/35625 ,  H03K3/012 ,  H03K3/0375

摘要： A flip flop circuit comprises a master latching circuit having a first transmission gate responsive to a clock signal and the complementary clock signal for transferring a data bit to a first positive feedback loop, and a slave latching circuit having a second transmission gate responsive to the clock signal and the complementary clock signal and complementarily shifted between on and off states with respect to the first transmission gate for transferring a data bit to a second positive feedback loop, wherein a buffer circuit is coupled between the first positive feedback loop and the first transmission gate so that the master flip flop circuit is free from influence of the slave flip flop circuit, thereby allowing a circuit designer to shrink set-up time margin.

摘要翻译： 触发器电路包括主锁存电路，其具有响应于时钟信号的第一传输门和用于将数据位传送到第一正反馈回路的互补时钟信号，以及具有响应于时钟的第二传输门的从锁存电路 信号和互补时钟信号，并相对于用于将数据位传送到第二正反馈环路的第一传输门口在导通和关断状态之间互补地移位，其中缓冲电路耦合在第一正反馈环路和第一传输门极 使得主触发器电路不受从触发器电路的影响，从而允许电路设计者收缩建立时间裕度。

公开(公告)号：US5223833A

公开(公告)日：1993-06-29

申请号：US770039

申请日：1991-10-02

申请人： Masao Akata

发明人： Masao Akata

IPC分类号： G11C19/00 ,  H03M9/00

CPC分类号： H03M9/00

摘要： A serial-parallel converting circuit comprises a four-stage shift register circuit receiving a serial data so as to shift the received serial data through the shift register in response to each clock signal, and an output register circuit coupled in parallel to respective stages of the shift register circuit so as to fetch the content of the shift register circuit in response to a frequency-divided clock supplied from a frequency dividing circuit. The frequency dividing circuit receives the clock signal through an inverter and is composed of only two D-type flipflops and one inverter. Each of the D-type flipflops has a clock input connected to receive the clock signal in common, and the D-type flipflops are connected in series to form a shifter register. A Q output of a second flipflop is connected through the inverter to a data input of a first flipflop, so that the Q output of the last flipflop generates the frequency-divided signal.

公开(公告)号：US5594724A

公开(公告)日：1997-01-14

申请号：US522555

申请日：1995-09-01

申请人： Masao Akata ,  Takao Miura ,  Takeshi Ogawa ,  Yukihiro Doi ,  Isao Higashi ,  Hitoshi Imagawa

发明人： Masao Akata ,  Takao Miura ,  Takeshi Ogawa ,  Yukihiro Doi ,  Isao Higashi ,  Hitoshi Imagawa

IPC分类号： H04Q3/00 ,  H04J3/00 ,  H04J3/16 ,  H04L12/64 ,  H04L12/951 ,  H04Q11/04 ,  H04L12/66

CPC分类号： H04Q11/0478 ,  H04J3/1611 ,  H04J2203/0089 ,  H04L2012/5647 ,  H04L2012/5673

摘要： A transmission convergence sublayer multiplex generating apparatus includes a TC layer calculating section, a TC layer information storing section for storing TC layer information in correspondence with each path, and an ATM layer information storing section for storing ATM layer information in correspondence with each path. The TC layer calculating section includes a section for, when receiving an ATM layer cell, storing the ATM layer cell in the ATM layer information storing section corresponding to a path number on the basis of header information of the ATM layer cell, and for, when receiving a TC layer information read request for each path through a control line, generating header error control information and scrambling the payload portion by time division multiplex processing using the ATM layer information of the corresponding path which is stored in the ATM layer information storing section to generate TC layer information, storing the TC layer information in the TC layer information storing section of the corresponding path, and outputting the TC layer information of the corresponding path to the TC layer information output line. A transmission convergence sublayer multiplex terminating apparatus is also disclosed.

摘要翻译： 发送汇聚子层多路复用生成装置包括：TC层计算部，与每个路径对应地存储TC层信息的TC层信息存储部，以及与各路对应地存储ATM层信息的ATM层信息存储部。 TC层计算部分包括一个部分，用于当接收到一个ATM层信元时，根据ATM层信元的报头信息将ATM层信元存储在与ATM数据信道对应的ATM层信息存储部分中， 通过控制线路接收每个路径的TC层信息读取请求，通过使用存储在ATM层信息存储部分中的对应路径的ATM层信息的时分多路复用处理产生报头错误控制信息和加扰有效负载部分， 生成TC层信息，将TC层信息存储在对应路径的TC层信息存储部中，并将对应路径的TC层信息输出到TC层信息输出行。 还公开了一种传输汇聚子层复用终端设备。

公开(公告)号：US5130975A

公开(公告)日：1992-07-14

申请号：US624556

申请日：1990-12-10

申请人： Masao Akata

发明人： Masao Akata

IPC分类号： H04L12/931

CPC分类号： H04L12/5601 ,  H04L49/106 ,  H04L49/255 ,  H04L49/405 ,  H04L2012/5679 ,  H04L2012/5681

摘要： An asynchronous transfer mode switching network system relays packets stored in packet buffer units to output ports designated by the packets, and a time slot scheduling unit assigns time slots to the packets stored in the packet buffer units upon arrival at the packet buffer units for preventing the packets from collision in a space division switching unit, wherein each of the packet buffer units sequentially writes new packets into respective memory locations but randomly reads out the new packets in the time slots assigned by the time slot scheduling unit so that the throughput of the space division switching unit is improved.