公开(公告)号：US07444612B2

公开(公告)日：2008-10-28

申请号：US11016988

申请日：2004-12-21

申请人： Masato Ariyama ,  Junko Taira ,  Kazuyuki Iida ,  Minoru Yabumoto ,  Tomohisa Suzuki ,  Minako Kubota

发明人： Masato Ariyama ,  Junko Taira ,  Kazuyuki Iida ,  Minoru Yabumoto ,  Tomohisa Suzuki ,  Minako Kubota

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： In designing integrated circuits such as FPGAs, a design support environment including the quality of design data is improved and the design efficiency is improved. An integrated-circuit design support apparatus that supports designing of an integrated circuit having a plurality of pins is provided. The apparatus includes a processor (a central processing unit) that forms a pin layout matrix (a matrix sheet) by unifying pin layout information of the integrated circuit using a common format and arranging the pin layout information in coordinates. The processor creates an integrated-circuit design library from the pin layout matrix.

摘要翻译： 在设计FPGA等集成电路时，提高了设计数据质量的设计支持环境，提高了设计效率。 提供一种支持具有多个引脚的集成电路的设计的集成电路设计支持装置。 该装置包括通过使用公共格式统一集成电路的引脚布局信息并且将引脚布局信息布置在坐标中来形成引脚布局矩阵（矩阵）的处理器（中央处理单元）。 处理器从引脚布局矩阵创建集成电路设计库。

公开(公告)号：US20060059447A1

公开(公告)日：2006-03-16

申请号：US11016988

申请日：2004-12-21

申请人： Masato Ariyama ,  Junko Taira ,  Kazuyuki Iida ,  Minoru Yabumoto ,  Tomohisa Suzuki ,  Minako Kubota

发明人： Masato Ariyama ,  Junko Taira ,  Kazuyuki Iida ,  Minoru Yabumoto ,  Tomohisa Suzuki ,  Minako Kubota

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： In designing integrated circuits such as FPGAs, a design support environment including the quality of design data is improved and the design efficiency is improved. An integrated-circuit design support apparatus that supports designing of an integrated circuit having a plurality of pins is provided. The apparatus includes a processor (a central processing unit) that forms a pin layout matrix (a matrix sheet) by unifying pin layout information of the integrated circuit using a common format and arranging the pin layout information in coordinates. The processor creates an integrated-circuit design library from the pin layout matri

摘要翻译： 在设计FPGA等集成电路时，提高了设计数据质量的设计支持环境，提高了设计效率。 提供一种支持具有多个引脚的集成电路的设计的集成电路设计支持装置。 该装置包括通过使用公共格式统一集成电路的引脚布局信息并且将引脚布局信息布置在坐标中来形成引脚布局矩阵（矩阵）的处理器（中央处理单元）。 处理器从引脚布局基础设施创建集成电路设计库

公开(公告)号：US5644500A

公开(公告)日：1997-07-01

申请号：US673472

申请日：1996-07-01

申请人： Hiroshi Miura ,  Masato Ariyama ,  Kazuyuki Iida ,  Kazufumi Iwahara ,  Mitsunobu Okano ,  Hiroyuki Orihara ,  Akira Katsumata ,  Toshiyasu Sakata ,  Masaharu Nishimura ,  Hirofumi Hamamura ,  Naoki Murakami ,  Mitsuru Yasuda ,  Yasuhiro Yamashita ,  Ryouji Yamada ,  Atsushi Yamane

发明人： Hiroshi Miura ,  Masato Ariyama ,  Kazuyuki Iida ,  Kazufumi Iwahara ,  Mitsunobu Okano ,  Hiroyuki Orihara ,  Akira Katsumata ,  Toshiyasu Sakata ,  Masaharu Nishimura ,  Hirofumi Hamamura ,  Naoki Murakami ,  Mitsuru Yasuda ,  Yasuhiro Yamashita ,  Ryouji Yamada ,  Atsushi Yamane

IPC分类号： H01L21/3205 ,  G06F17/50 ,  H01L21/82 ,  H01L23/52 ,  G06F15/00

CPC分类号： G06F17/5072 ,  G06F17/5077

摘要： This invention is directed to a method and apparatus to find out an optimum solution in automatic routing or automatic placement with certainty and at a high-speed to improve a routing rate, and to realize automatic routing in a high-density. To these end, a routing approach is selected in a conversational mode while routing efficiency is consulted to compose routing processing procedure so as to generate a routing program. Besides, component placement processing procedures designated according to placement control information are combined to generate the placement program. A straight line between component pins adjacent to each other is defined as a chord, a wave for maze method routing is generated from a start point toward an end point of a routing path and propagated between the chords adjacent to each other. Positions of the chords through which the wave has passed until reaching the end point from the start point are successively stored and the positions through which the wave has passed is traced back to the start point from the end point when the wave reaches the end point to decide a routing path of the routing pattern. The method and apparatus of this invention are applicable to routing design or component placement design of LSIs, multichip modules, printed circuit boards, etc.

摘要翻译： 本发明涉及一种以确定性和高速度找出自动路由或自动放置的最佳方案以提高路由速率并实现高密度自动路由的方法和装置。 为此，在会话模式中选择路由选择方法，同时查询路由效率以组合路由处理过程，以便生成路由程序。 此外，组合根据放置控制信息指定的部件布置处理程序以生成放置程序。 彼此相邻的部件销之间的直线被定义为和弦，从起点到路径路径的终点产生迷宫方法路由的波，并且在彼此相邻的和弦之间传播。 通过波过去的和弦直到从起点到达终点的弦的位置被连续地存储，并且当波到达终点时波已经通过的位置从终点被追溯到起点 决定路由模式的路由路径。 本发明的方法和装置可应用于LSI，多芯片模块，印刷电路板等的布线设计或组件放置设计。

公开(公告)号：US20120079445A1

公开(公告)日：2012-03-29

申请号：US13215486

申请日：2011-08-23

申请人： Masato Ariyama ,  Kazuhiro Sakai

发明人： Masato Ariyama ,  Kazuhiro Sakai

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： A circuit board designing device has a database that stores an another-component arrangement forbidden range table, a related component information table, and a relative-arranging position table, and a processing unit that executes arrangement of the components, determines the another-component arrangement forbidden range which is set to forbid arrangement of another component in the predetermined range on the basis of the arranging position of the basic component with reference to the another-component arrangement forbidden range table when arrangement of the basic component is instructed, acquires related component information corresponding to the related component to be combined with the basic components with reference to the related component information table, acquires a relative-arranging position of the related component from the relative-arranging position table on the basis of the acquired related component information, and sets the acquired related component in the another-component arrangement forbidden range when a predetermined condition is satisfied.

摘要翻译： 电路板设计装置具有存储另一组件布置禁止范围表的数据库，相关组件信息表和相对排列位置表以及执行组件的布置的处理单元，确定另一组件布置 禁止范围，其被设定为在指示了基本部件的布置时，参照基本部件的配置禁止范围表，基于基本部件的布置位置，在预定范围内禁止布置其他部件，获取相关部件信息 对应于要与基本部件组合的相关部件参照相关部件信息表，根据所获取的相关部件信息从相对位置表获取相关部件的相对排列位置，并设置 在另一家公司获得的相关组件 当满足预定条件时，组件布置禁止范围。

公开(公告)号：US09261875B2

公开(公告)日：2016-02-16

申请号：US13595238

申请日：2012-08-27

申请人： Masato Ariyama ,  Kazuhiro Sakai

发明人： Masato Ariyama ,  Kazuhiro Sakai

IPC分类号： G06F17/50 ,  G05B19/4097

CPC分类号： G05B19/4097

摘要： A design-support-apparatus includes a storage unit that stores mounting information on an order of manufacturing processes, first-region-information indicating a region to be secured in mounting of each component on the substrate, second-region-information indicating a region occupied when each component is mounted on the substrate, a discrimination unit configured to determine a before-and-after relationship between manufacturing processes of mounting a first-component and a second-component that are arranged on the substrate, an acquisition unit configured to acquire the first-region-information for the component of which the manufacturing process is determined to be later by the discrimination unit between the first component and the second-component and acquire the second-region-information for the component of which the manufacturing process is determined to be earlier, and a determination unit configured to compare the first-region-information and the second-region-information so as to determine presence of interference.

摘要翻译： 设计支持装置包括存储单元，其存储关于制造过程的顺序的安装信息，指示在每个部件安装在基板上时要固定的区域的第一区域信息，指示所占据的区域的第二区域信息 当每个部件安装在基板上时，识别单元被配置为确定安装布置在基板上的第一部件和第二部件的安装的制造过程之间的之前和之后的关系;获取单元，被配置为获取 通过第一部件和第二部件之间的识别单元确定制造过程的稍后的部件的第一区域信息，并且获取其制造过程被确定的部件的第二区域信息 以及确定单元，被配置为比较第一区域信息和第二区域信息 以确定干扰的存在。

公开(公告)号：US6117183A

公开(公告)日：2000-09-12

申请号：US894695

申请日：1997-08-26

申请人： Mieko Teranishi ,  Yoshiyuki Iwakura ,  Masaharu Nishimura ,  Akira Katsumata ,  Masato Ariyama

发明人： Mieko Teranishi ,  Yoshiyuki Iwakura ,  Masaharu Nishimura ,  Akira Katsumata ,  Masato Ariyama

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F17/5068

摘要： Disclosed is an interactive CAD apparatus for logic circuit packaging design, wherein provisions are made to display delay times in real time when a component is being moved, so that error-contributing components and interconnections can be easily identified and the optimum position can be easily determined. The apparatus includes: a component moving unit, responsive to an operator's instruction, for moving a component on a display screen where a component placement diagram is displayed; an associated path extraction unit for extracting a signal path associated with the component being moved by the component moving unit; a temporary position calculation unit for calculating temporary position data representing a placement position corresponding to the position of the component on the display screen at prescribed intervals of time when the component is being moved by the component moving unit; an associated path delay calculation unit for successively calculating delay values for the signal path extracted by the associated path extraction unit, based on the temporary position data calculated by the temporary position calculation unit; and an associated path delay display unit for successively displaying the delay values calculated by the associated path delay calculation unit.

摘要翻译： PCT No.PCT / JP97 / 00015 Sec。 371日期：1997年8月26日 102（e）日期1997年8月26日PCT 1997年1月8日PCT公布。 公开号WO97 / 25681 日期1997年7月17日公开是一种用于逻辑电路封装设计的交互式CAD设备，其中规定了在组件移动时实时显示延迟时间，从而可以容易地识别出错误的组件和互连，并且最优 位置可以很容易地确定。 该装置包括：组件移动单元，响应于操作者的指示，用于移动显示屏幕上的组件，其中显示组件放置图; 相关联的路径提取单元，用于提取与由所述分量移动单元移动的分量相关联的信号路径; 临时位置计算单元，用于当由所述分量移动单元移动所述分量时，以规定的时间间隔计算表示与所述分量在所述显示屏幕上的位置相对应的放置位置的临时位置数据; 相关联的路径延迟计算单元，用于基于由临时位置计算单元计算的临时位置数据连续地计算由相关联的路径提取单元提取的信号路径的延迟值; 以及相关联的路径延迟显示单元，用于连续显示由相关联的路径延迟计算单元计算的延迟值。