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公开(公告)号：US07319420B2
公开(公告)日：2008-01-15
申请号：US11338651
申请日：2006-01-25
IPC分类号： H03M3/00
摘要： A cascade-type variable-order delta-sigma modulator with low power consumption that can change the number of stages of the quantization loops, which are connected in a cascade configuration, to an optimum number depending on peripheral circuitries in a configuration as simple as possible. The present invention includes first to nth stages of delta-sigma modulating type quantization loops (n is an integer equal to or more than 2) connected in a cascade configuration, and a noise rejecting circuit. Each quantization loop quantizes an input signal, outputs the quantization result, and feeds back the quantization result to itself. The noise rejecting circuit rejects a quantization noise of the first stage of quantization loop, and comprises (n−1) selectors for activating and de-activating the respective output signals of the second and succeeding stages of the quantization loops in compliance with the control signal.
摘要翻译： 具有低功耗的级联型可变阶Δ-Σ调制器，其可以将串联配置中连接的量化循环的级数改变为最佳数量，这取决于尽可能简单的配置中的外设电路 。 本发明包括以级联配置连接的Δ-Σ调制型量化环（n为等于或大于2的整数）的第一至第N级，以及噪声抑制电路。 每个量化环对输入信号进行量化，输出量化结果，并将量化结果反馈给自身。 噪声抑制电路拒绝量化环路的第一级的量化噪声，并且包括用于根据控制信号激活和去激活量化环路的第二级和后级的各个输出信号的（n-1）个选择器 。
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公开(公告)号：US20060164274A1
公开(公告)日：2006-07-27
申请号：US11338651
申请日：2006-01-25
IPC分类号： H03M3/00
摘要： A cascade-type variable-order delta-sigma modulator with low power consumption that can change the number of stages of the quantization loops, which are connected in a cascade configuration, to an optimum number depending on peripheral circuitries in a configuration as simple as possible. The present invention includes first to nth stages of delta-sigma modulating type quantization loops (n is an integer equal to or more than 2) connected in a cascade configuration, and a noise rejecting circuit. Each quantization loop quantizes an input signal, outputs the quantization result, and feeds back the quantization result to itself. The noise rejecting circuit rejects a quantization noise of the first stage of quantization loop, and comprises (n−1) selectors for activating and de-activating the respective output signals of the second and succeeding stages of the quantization loops in compliance with the control signal.
摘要翻译： 具有低功耗的级联型可变阶Δ-Σ调制器，其可以将串联配置中连接的量化循环的级数改变为最佳数量，这取决于尽可能简单的配置中的外设电路 。 本发明包括以级联配置连接的Δ-Σ调制型量化环（n为等于或大于2的整数）的第一至第N级，以及噪声抑制电路。 每个量化环对输入信号进行量化，输出量化结果，并将量化结果反馈给自身。 噪声抑制电路拒绝量化环路的第一级的量化噪声，并且包括用于根据控制信号激活和去激活量化环路的第二级和后级的各个输出信号的（n-1）个选择器 。
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公开(公告)号：US20070159557A1
公开(公告)日：2007-07-12
申请号：US11617362
申请日：2006-12-28
IPC分类号： H04N5/14
CPC分类号： H04N5/148 , H04N5/60 , H04N21/41407 , H04N21/42607
摘要： A semiconductor integrated circuit includes an audio signal amplifier and a video signal amplifier built in a single semiconductor chip, the audio signal amplifier and the video signal amplifier being configured to receive a supply of a positive power supply voltage and a negative power supply voltage. The semiconductor integrated circuit further includes a negative voltage generation circuit that generates the negative power supply voltage and supplies the negative power supply voltage to the audio signal amplifier and the video signal amplifier and a limit circuit that limits an amplitude of a signal input to the audio signal amplifier to a range free from an influence of a fluctuation in the negative power supply voltage supplied by the negative voltage generation circuit. Adverse effects on an audio signal due to a fluctuation of a negative voltage occurring in synchronization with the vertical period of a video signal can be suppressed with a simple additional circuit.
摘要翻译： 半导体集成电路包括内置在单个半导体芯片中的音频信号放大器和视频信号放大器，音频信号放大器和视频信号放大器被配置为接收正电源电压和负电源电压的供给。 半导体集成电路还包括产生负电源电压并将负电源电压提供给音频信号放大器和视频信号放大器的负电压产生电路，以及限制输入到音频的信号的幅度的限制电路 信号放大器到不受负电压产生电路提供的负电源电压的波动的影响的范围内。 通过简单的附加电路可以抑制由于与视频信号的垂直周期同步而产生的负电压的波动对音频信号的不利影响。
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公开(公告)号：US07646245B2
公开(公告)日：2010-01-12
申请号：US11876285
申请日：2007-10-22
申请人： Masato Nakakita , Makoto Yamamoto
发明人： Masato Nakakita , Makoto Yamamoto
IPC分类号： H03F3/10
CPC分类号： H03G3/3026
摘要： An amplifier includes: a single-stage or multiple-stage variable gain amplifier that amplifies an input signal with a controlled gain; a AGC control circuit that detects the peak level of a signal outputted from the variable gain amplifier in the final stage, converts the resultant signal to a digital signal, and outputs an AGC control signal for controlling the gain of the variable gain amplifier based on the converted digital signal; an EVR control circuit that outputs an EVR control signal according to a signal of setting an attenuation value or an amplification value for EVR inputted from an electronic variable resistor control terminal; and a gain control circuit that controls the gain of the variable gain amplifier in accordance with at least one of the AGC control signal and the EVR control signal. The occurrence of “popping” sounds caused by differences in DC voltage due to switching between an AGC circuit and an electronic variable resistor circuit can be suppressed.
摘要翻译： 放大器包括：单级或多级可变增益放大器，其以受控增益放大输入信号; AGC控制电路，检测在最终级中从可变增益放大器输出的信号的峰值电平，将得到的信号转换为数字信号，并输出用于控制可变增益放大器的增益的AGC控制信号，该AGC控制信号基于 转换数字信号; EVR控制电路，其根据从电子可变电阻控制端子输入的用于EVR的衰减值或放大值的信号输出EVR控制信号; 以及增益控制电路，其根据AGC控制信号和EVR控制信号中的至少一个控制可变增益放大器的增益。 可以抑制由AGC电路和电子可变电阻电路之间的切换引起的直流电压的差异引起的“爆”声。
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公开(公告)号：US20080129387A1
公开(公告)日：2008-06-05
申请号：US11876285
申请日：2007-10-22
申请人： Masato Nakakita , Makoto Yamamoto
发明人： Masato Nakakita , Makoto Yamamoto
IPC分类号： H03G3/32
CPC分类号： H03G3/3026
摘要： An amplifier includes: a single-stage or multiple-stage variable gain amplifier that amplifies an input signal with a controlled gain; a AGC control circuit that detects the peak level of a signal outputted from the variable gain amplifier in the final stage, converts the resultant signal to a digital signal, and outputs an AGC control signal for controlling the gain of the variable gain amplifier based on the converted digital signal; an EVR control circuit that outputs an EVR control signal according to a signal of setting an attenuation value or an amplification value for EVR inputted from an electronic variable register control terminal; and a gain control circuit that controls the gain of the variable gain amplifier in accordance with at least one of the AGC control signal and the EVR control signal. The occurrence of “popping” sounds caused by differences in DC voltage due to switching between an AGC circuit and an electronic variable register circuit can be suppressed.
摘要翻译： 放大器包括：单级或多级可变增益放大器，其以受控增益放大输入信号; AGC控制电路，检测在最终级中从可变增益放大器输出的信号的峰值电平，将得到的信号转换为数字信号，并输出用于控制可变增益放大器的增益的AGC控制信号，该AGC控制信号基于 转换数字信号; EVR控制电路，其根据从电子可变寄存器控制端子输入的用于EVR的衰减值或放大值的信号输出EVR控制信号; 以及增益控制电路，其根据AGC控制信号和EVR控制信号中的至少一个控制可变增益放大器的增益。 可以抑制由于AGC电路和电子可变寄存器电路之间的切换而导致的直流电压差异引起的“弹出”声音的发生。
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