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公开(公告)号：US20060164274A1
公开(公告)日：2006-07-27
申请号：US11338651
申请日：2006-01-25
IPC分类号： H03M3/00
摘要： A cascade-type variable-order delta-sigma modulator with low power consumption that can change the number of stages of the quantization loops, which are connected in a cascade configuration, to an optimum number depending on peripheral circuitries in a configuration as simple as possible. The present invention includes first to nth stages of delta-sigma modulating type quantization loops (n is an integer equal to or more than 2) connected in a cascade configuration, and a noise rejecting circuit. Each quantization loop quantizes an input signal, outputs the quantization result, and feeds back the quantization result to itself. The noise rejecting circuit rejects a quantization noise of the first stage of quantization loop, and comprises (n−1) selectors for activating and de-activating the respective output signals of the second and succeeding stages of the quantization loops in compliance with the control signal.
摘要翻译： 具有低功耗的级联型可变阶Δ-Σ调制器，其可以将串联配置中连接的量化循环的级数改变为最佳数量，这取决于尽可能简单的配置中的外设电路 。 本发明包括以级联配置连接的Δ-Σ调制型量化环（n为等于或大于2的整数）的第一至第N级，以及噪声抑制电路。 每个量化环对输入信号进行量化，输出量化结果，并将量化结果反馈给自身。 噪声抑制电路拒绝量化环路的第一级的量化噪声，并且包括用于根据控制信号激活和去激活量化环路的第二级和后级的各个输出信号的（n-1）个选择器 。
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公开(公告)号：US07319420B2
公开(公告)日：2008-01-15
申请号：US11338651
申请日：2006-01-25
IPC分类号： H03M3/00
摘要： A cascade-type variable-order delta-sigma modulator with low power consumption that can change the number of stages of the quantization loops, which are connected in a cascade configuration, to an optimum number depending on peripheral circuitries in a configuration as simple as possible. The present invention includes first to nth stages of delta-sigma modulating type quantization loops (n is an integer equal to or more than 2) connected in a cascade configuration, and a noise rejecting circuit. Each quantization loop quantizes an input signal, outputs the quantization result, and feeds back the quantization result to itself. The noise rejecting circuit rejects a quantization noise of the first stage of quantization loop, and comprises (n−1) selectors for activating and de-activating the respective output signals of the second and succeeding stages of the quantization loops in compliance with the control signal.
摘要翻译： 具有低功耗的级联型可变阶Δ-Σ调制器，其可以将串联配置中连接的量化循环的级数改变为最佳数量，这取决于尽可能简单的配置中的外设电路 。 本发明包括以级联配置连接的Δ-Σ调制型量化环（n为等于或大于2的整数）的第一至第N级，以及噪声抑制电路。 每个量化环对输入信号进行量化，输出量化结果，并将量化结果反馈给自身。 噪声抑制电路拒绝量化环路的第一级的量化噪声，并且包括用于根据控制信号激活和去激活量化环路的第二级和后级的各个输出信号的（n-1）个选择器 。
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3.发明申请INERTIAL VELOCITY SENSOR SIGNAL PROCESSING CIRCUIT AND INERTIAL VELOCITY SENSOR DEVICE INCLUDING THE SAME 审中-公开惯性速度传感器信号处理电路和包括其中的惯性速度传感器装置公开(公告)号：US20100126271A1
公开(公告)日：2010-05-27
申请号：US12599008
申请日：2008-10-30
申请人： Fumihito Inukai , Hitoshi Kobayashi
发明人： Fumihito Inukai , Hitoshi Kobayashi
IPC分类号： G01C19/56
CPC分类号： G01C19/5607 , G01C19/56
摘要： An inertial velocity sensor signal processing circuit (12, 13, 14) used together with an inertial velocity sensor element (11) includes a first signal processing circuit (12, 13) which operates with a first clock (CLK1) and a second signal processing circuit (14) which operates with a second clock (CLK2) which does not synchronize with the first clock.
摘要翻译： 与惯性速度传感器元件（11）一起使用的惯性速度传感器信号处理电路（12,13,14）包括第一信号处理电路（12,13），其以第一时钟（CLK1）和第二信号处理 电路（14），其以与第一时钟不同步的第二时钟（CLK2）操作。
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公开(公告)号：US07084797B2
公开(公告)日：2006-08-01
申请号：US10973254
申请日：2004-10-27
IPC分类号： H03M3/00
CPC分类号： H03M3/418
摘要： A first second- or higher-order delta sigma modulator and a second second- or higher-order delta sigma modulator having a notch characteristic are cascaded together, and a delayed signal of the output of the first delta sigma modulator and a differential signal of the output of the second delta sigma modulator are added together. The amount of feedback from the output portion to the input portion of the first delta sigma modulator and the amount of feedback from the output portion to the input portion of the second delta sigma modulator are made the same.
摘要翻译： 具有陷波特性的第一第二或更高阶ΔΣ调制器和第二二阶或更高阶ΔΣ调制器级联在一起，并且第一ΔΣ调制器的输出的延迟信号和 将第二ΔΣ调制器的输出相加在一起。 使得从第一Δ-Σ调制器的输出部分到输入部分的反馈量和从第二ΔΣ调制器的输出部分到输入部分的反馈量相同。
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公开(公告)号：US07439893B2
公开(公告)日：2008-10-21
申请号：US11776748
申请日：2007-07-12
申请人： Fumihito Inukai , Hitoshi Kobayashi
发明人： Fumihito Inukai , Hitoshi Kobayashi
IPC分类号： H03M3/00
CPC分类号： H03M7/3022 , H03F3/2175 , H03M7/3042
摘要： By using a selector, an output of a delta sigma modulator having a quantizer for quantizing a signal is selectively supplied to one of a first D/A converter having a linear amplifier and a second D/A converter having a digital amplifier. Further, the number of quantization levels of the quantizer, the sampling frequency, or the order of a transfer function of the delta sigma modulator is selected by a control signal selector in conjunction with the selector. An output of the first D/A converter is supplied to a line terminal, while an output of the second D/A converter is supplied to a headphone terminal.
摘要翻译： 通过使用选择器，具有用于量化信号的量化器的Δ-Σ调制器的输出被选择性地提供给具有线性放大器的第一D / A转换器和具有数字放大器的第二D / A转换器之一。 此外，控制信号选择器与选择器一起选择量化器的量化级数，采样频率或ΔΣ调制器的传递函数的阶数。 第一D / A转换器的输出被提供给线路终端，而第二D / A转换器的输出被提供给耳机终端。
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公开(公告)号：US07636056B2
公开(公告)日：2009-12-22
申请号：US12124079
申请日：2008-05-20
申请人： Fumihito Inukai , Hitoshi Kobayashi
发明人： Fumihito Inukai , Hitoshi Kobayashi
IPC分类号： H03M3/00
摘要： In a delta sigma modulator including first and second integration circuits connected in cascade, each as a component thereof, first and second power source terminals for supplying first and second different power source voltages to the first and second integration circuits are provided. The first power source voltage is supplied to the former-stage first integration circuit having a SNR which is largely affected by the magnitude of the power source voltage. The second power source voltage lower than the first power source voltage is supplied to the latter-stage second integration circuit having a SNR which is not largely affected by the magnitude of the power source voltage.
摘要翻译： 在包括串联连接的第一和第二积分电路的三角Σ调制器中，每个作为其组成部分，提供用于向第一和第二积分电路提供第一和第二不同电源电压的第一和第二电源端子。 第一电源电压被提供给前级第一积分电路，其具有很大程度上受电源电压幅度影响的SNR。 低于第一电源电压的第二电源电压被提供给具有不受电源电压的大小的很大影响的SNR的后级第二积分电路。
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公开(公告)号：US06954161B2
公开(公告)日：2005-10-11
申请号：US10865885
申请日：2004-06-14
摘要： A delta-sigma modulation quantization loop, comprising an integration circuit for integrating the difference between an analog input signal and a feedback reference voltage, a local quantizer for quantizing the output of the integration circuit into a digital signal, and a DA converter for generating the feedback reference voltage from the digital output of the local quantizer, is used as a single stage, and a plurality of the stages are cascade-connected. In the second-stage and subsequent modulation quantization loops, the difference signal between the input of the local quantizer of the previous stage and the output of the DA converter of the previous stage is used as an analog input signal. The feedback reference voltages of the respective delta-sigma modulation quantization loops are set individually so as to be higher than the specified maximum voltage of the analog input signal to limit the gains of the respective delta-sigma modulation quantization loops. Gain setting devices are provided in a noise reduction circuit to roughly compensate the gains limited in the respective delta-sigma modulation quantization loops.
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公开(公告)号：US20050088327A1
公开(公告)日：2005-04-28
申请号：US10973254
申请日：2004-10-27
CPC分类号： H03M3/418
摘要： A first second- or higher-order delta sigma modulator and a second second- or higher-order delta sigma modulator having a notch characteristic are cascaded together, and a delayed signal of the output of the first delta sigma modulator and a differential signal of the output of the second delta sigma modulator are added together. The amount of feedback from the output portion to the input portion of the first delta sigma modulator and the amount of feedback from the output portion to the input portion of the second delta sigma modulator are made the same.
摘要翻译： 具有陷波特性的第一第二或更高阶ΔΣ调制器和第二二阶或更高阶ΔΣ调制器级联在一起，并且第一ΔΣ调制器的输出的延迟信号和 将第二ΔΣ调制器的输出相加在一起。 使得从第一Δ-Σ调制器的输出部分到输入部分的反馈量和从第二ΔΣ调制器的输出部分到输入部分的反馈量相同。
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公开(公告)号：US20050001751A1
公开(公告)日：2005-01-06
申请号：US10865885
申请日：2004-06-14
摘要： A delta-sigma modulation quantization loop, comprising an integration circuit for integrating the difference between an analog input signal and a feedback reference voltage, a local quantizer for quantizing the output of the integration circuit into a digital signal, and a DA converter for generating the feedback reference voltage from the digital output of the local quantizer, is used as a single stage, and a plurality of the stages are cascade-connected. In the second-stage and subsequent modulation quantization loops, the difference signal between the input of the local quantizer of the previous stage and the output of the DA converter of the previous stage is used as an analog input signal. The feedback reference voltages of the respective delta-sigma modulation quantization loops are set individually so as to be higher than the specified maximum voltage of the analog input signal to limit the gains of the respective delta-sigma modulation quantization loops. Gain setting devices are provided in a noise reduction circuit to roughly compensate the gains limited in the respective delta-sigma modulation quantization loops.
摘要翻译： 一种Δ-Σ调制量化环路，包括用于对模拟输入信号和反馈参考电压之间的差异进行积分的积分电路，用于将积分电路的输出量化为数字信号的局部量化器，以及用于产生 来自本地量化器的数字输出的反馈参考电压被用作单级，并且多级级联连接。 在第二级和随后的调制量化环路中，前级的本地量化器的输入与前一级的DA转换器的输出之间的差分信号用作模拟输入信号。 相应的Δ-Σ调制量化环路的反馈参考电压被分别设置为高于模拟输入信号的规定的最大电压以限制相应的Δ-Σ调制量化环路的增益。 在降噪电路中提供增益设置装置，以大致补偿在相应的Δ-Σ调制量化环路中限制的增益。
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10.发明授权公开(公告)号：US08013647B2
公开(公告)日：2011-09-06
申请号：US12621837
申请日：2009-11-19
申请人： Fumihito Inukai , Seiichi Muroya , Yoichi Kaino
发明人： Fumihito Inukai , Seiichi Muroya , Yoichi Kaino
IPC分类号： H03L7/00
CPC分类号： G01C19/5607 , G01P15/125
摘要： A physical quantity detection circuit (12) is used for a physical quantity sensor (10) that outputs a sensor signal according to a physical quantity given externally. A phase adjustment circuit (100) receives a reference clock (CKref) and operates in synchronization with an operation clock (CKa), to delay a transition edge of the reference clock by a predetermined number of pulses of the operation clock. A detection circuit (104) detects a physical quantity signal from the sensor signal (Ssnc) using a transition edge of a clock (SSS) from the phase adjustment circuit (100) as the reference.
摘要翻译： 物理量检测电路（12）用于根据外部给出的物理量输出传感器信号的物理量传感器（10）。 相位调整电路（100）接收参考时钟（CKref）并与操作时钟（CKa）同步地操作，以将参考时钟的转换边缘延迟预定数量的操作时钟的脉冲。 检测电路（104）使用来自相位调整电路（100）的时钟（SSS）的转移边缘作为基准，从传感器信号（Ssnc）检测物理量信号。
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