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公开(公告)号：US07124283B2
公开(公告)日：2006-10-17
申请号：US10457409
申请日：2003-06-10
申请人： Tetsuya Yamada , Naohiko Irie , Takanobu Tsunoda , Takahiro Irita , Keisuke Toyama , Masayuki Kabasawa
发明人： Tetsuya Yamada , Naohiko Irie , Takanobu Tsunoda , Takahiro Irita , Keisuke Toyama , Masayuki Kabasawa
IPC分类号： G06F5/00
CPC分类号： G06F9/3879 , G06F9/30174 , G06F9/4552
摘要： The present invention provides a hardware accelerator, which allows faster switching between processing modes. In an information processing device with a bytecode accelerator BCA for translating a stack-based intermediate code (bytecode) into register-based instructions, a selector SEL for switching between BCA and soft VM is posed between an instruction part FET and a decode part DEC and data transfer paths P4 and P5 are formed between BCA and the register file REG_FILE. When bytecode accelerator BCA is activated, the P3 side is selected by the selector SEL and the translated CPU instructions are transferred to the decode part DEC. If the intermediate language code cannot be translated by the BCA, the processing mode is switched to software processing. During switching between the modes, internal information of BCA can be transferred between BCA and REG_FILE in parallel, achieving faster mode switching.
摘要翻译： 本发明提供一种硬件加速器，其允许在处理模式之间更快地切换。 在具有用于将基于堆栈的中间码（字节码）转换为基于寄存器的指令的字节码加速器BCA的信息处理装置中，在指令部分FET和解码部分DEC之间存在用于在BCA和软VM之间切换的选择器SEL， 在BCA和寄存器文件REG_FILE之间形成数据传送路径P 4和P 5。 当字节码加速器BCA被激活时，选择器SEL选择P 3侧，转换的CPU指令被传送到解码部分DEC。 如果BCA不能翻译中间语言代码，则将处理模式切换到软件处理。 在模式切换期间，BCA的内部信息可以在BCA和REG_FILE之间并行传输，实现更快的模式切换。
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2.发明授权Method and apparatus for event detection for multiple instruction-set processor 有权多指令集处理器的事件检测方法和装置公开(公告)号：US07493479B2
公开(公告)日：2009-02-17
申请号：US10458289
申请日：2003-06-11
CPC分类号： G06F9/30174 , G06F9/3851
摘要： A method and apparatus are provided for event detection for a multiple instruction-set processor. In one example of the apparatus, a data processing device comprises an instruction execution device configured to execute a first instruction set as specific instructions; an instruction conversion circuit configured to convert instructions of a second instruction set into a first instruction string of the first instruction set, and further configured to supply the first instruction string to the instruction execution device; and a counter device configured to count a prescribed event, wherein the instruction conversion circuit is further configured to output a prescribed instruction when the counter device is satisfied by a prescribed condition.
摘要翻译： 提供了一种用于多指令集处理器的事件检测的方法和装置。 在该装置的一个示例中，数据处理装置包括被配置为执行第一指令集作为特定指令的指令执行装置; 指令转换电路，被配置为将第二指令集的指令转换为第一指令集的第一指令串，并且还被配置为将第一指令串提供给指令执行装置; 以及计数器装置，被配置为对规定的事件进行计数，其中所述指令转换电路还被配置为当所述计数器装置满足规定条件时输出规定的指令。
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3.发明授权Information processing device having arrangements to inhibit coprocessor upon encountering data that the coprocessor cannot handle 失效信息处理装置具有在遇到协处理器不能处理的数据时禁止协处理器的装置公开(公告)号：US07788469B2
公开(公告)日：2010-08-31
申请号：US10883758
申请日：2004-07-06
IPC分类号： G06F15/76
CPC分类号： G06F9/30174 , G06F9/30014 , G06F9/3861 , G06F9/3877 , G06F9/3879
摘要： A hardware accelerator is used to execute a floating-point byte-code in an information processing device. For a floating-point byte-code, a byte-code accelerator BCA feeds an instruction stream for using a FPU to a CPU. When the FPU is used, first the data is transferred to the FPU register from a general-purpose register, and then an FPU operation is performed. For data, such as a denormalized number, that cannot be processed by the FPU, in order to call a floating-point math library of software, the processing of the BCA is completed and the processing moves to processing by software. In order to realize this, data on a data transfer bus from the CPU to the FPU is snooped by the hardware accelerator, and a cancel request is signaled to the CPU to inhibit execution of the FPU operation when corresponding data is detected in a data checking part.
摘要翻译： 硬件加速器用于在信息处理设备中执行浮点字节码。 对于浮点字节码，字节码加速器BCA将用于使用FPU的指令流馈送到CPU。 当使用FPU时，首先将数据从通用寄存器传送到FPU寄存器，然后执行FPU操作。 对于不能由FPU处理的数据，如非规范化数字，为了调用软件的浮点数学库，BCA的处理完成，并且处理转移到软件处理。 为了实现这一点，由硬件加速器窥探从CPU到FPU的数据传输总线上的数据，并且当在数据检查中检测到对应的数据时，向CPU发送取消请求以禁止执行FPU操作 部分。
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公开(公告)号：US20050027965A1
公开(公告)日：2005-02-03
申请号：US10883758
申请日：2004-07-06
CPC分类号： G06F9/30174 , G06F9/30014 , G06F9/3861 , G06F9/3877 , G06F9/3879
摘要： A hardware accelerator is used to execute a floating-point byte-code in an information processing device. For a floating-point byte-code, a byte-code accelerator BCA feeds an instruction stream for using a FPU to a CPU. When the FPU is used, first the data is transferred to the FPU register from a general-purpose register, and then an FPU operation is performed. For data, such as a denormalized number, that cannot be processed by the FPU, in order to call a floating-point math library of software, the processing of the BCA is completed and the processing moves to processing by software. In order to realize this, data on a data transfer bus from the CPU to the FPU is snooped by the hardware accelerator, and a cancel request is signaled to the CPU to inhibit execution of the FPU operation when 4corresponding data is detected in a data checking part.
摘要翻译： 硬件加速器用于在信息处理设备中执行浮点字节码。 对于浮点字节码，字节码加速器BCA将用于使用FPU的指令流馈送到CPU。 当使用FPU时，首先将数据从通用寄存器传送到FPU寄存器，然后执行FPU操作。 对于不能由FPU处理的数据，如非规范化数字，为了调用软件的浮点数学库，BCA的处理完成，并且处理转移到软件处理。 为了实现这一点，由硬件加速器监视从CPU到FPU的数据传输总线上的数据，并且当在数据检查中检测到4个对应数据时，向CPU发送取消请求以禁止执行FPU操作 部分。
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公开(公告)号：US20100021085A1
公开(公告)日：2010-01-28
申请号：US12460323
申请日：2009-07-16
申请人： Masayuki Kabasawa
发明人： Masayuki Kabasawa
IPC分类号： G06K9/32
CPC分类号： G06T3/4084
摘要： Disclosed herein is an image processing apparatus, including an expansion section configured to expand an input image by interpolation using peripheral pixel values; a positioning section configured to carry out positioning of an expanded image obtained by expansion of the input image and an output image obtained in an immediately preceding operation cycle; a separation section configured to separate the output image into low frequency components and high frequency components; and a mixture-addition section configured to mix the low frequency components with the expanded image and add the high frequency components to the image obtained by the mixture to produce a new output image.
摘要翻译： 本文公开了一种图像处理装置，包括：扩展部，被配置为通过使用周边像素值进行插值来扩展输入图像; 定位部，被配置为执行通过输入图像的扩展获得的扩展图像的定位和在前一操作周期中获得的输出图像; 分离部，被配置为将输出图像分离成低频分量和高频分量; 以及混合添加部分，被配置为将低频分量与扩展图像混合，并将高频分量加到由混合物获得的图像中以产生新的输出图像。
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公开(公告)号：US08406572B2
公开(公告)日：2013-03-26
申请号：US12460323
申请日：2009-07-16
申请人： Masayuki Kabasawa
发明人： Masayuki Kabasawa
CPC分类号： G06T3/4084
摘要： Disclosed herein is an image processing apparatus, including an expansion section configured to expand an input image by interpolation using peripheral pixel values; a positioning section configured to carry out positioning of an expanded image obtained by expansion of the input image and an output image obtained in an immediately preceding operation cycle; a separation section configured to separate the output image into low frequency components and high frequency components; and a mixture-addition section configured to mix the low frequency components with the expanded image and add the high frequency components to the image obtained by the mixture to produce a new output image.
摘要翻译： 这里公开了一种图像处理装置，包括：扩展部，被配置为通过使用周边像素值进行插值来扩展输入图像; 定位部，被配置为执行由输入图像的扩展获得的扩大图像和在紧接在前的操作周期中获得的输出图像的定位; 分离部，被配置为将输出图像分离成低频分量和高频分量; 以及混合添加部分，被配置为将低频分量与扩展图像混合，并将高频分量加到由混合物获得的图像中以产生新的输出图像。
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